Hi Regarding the Verilog source, I would start with the next steps: 1. convert the test scripts to bash or better Makefile 2. rerun the tests (simulation) 3. rerun Xilinx ISE build scripts 4. put RTL and simulation files into separate directories 5. review the code to find Xilinx specifics, for now only a memory, which can be written generically
Regarding code portability, usually the platform specific code is for: - internal memories - PLL, other clocking related details, this is never portable - IO, if specific IO features are used - 3rd party IP, for example an external memory controller, this is related to IO I can generalize memories, here I have experience with Altera Quartus, Xilinx Vivado and Synplify (used but Lattice). The code will have to be organized into portable and non portable segments. Here portability depends on the FPGA vendor and the board feature set. Then for every board top level files are created containing the list of IOs. Inside top level modules, generic modules are instantiated, potentially with some device specific code added (PLL). All FPGA vendors have tools for Linux, and all tools support scripted build processes. So building a release can be automatized, to avoid human error. I usually only have issues while migrating to newer tool versions. I would also suggest using Verilog 2001, it is especially useful to avoid repetition in port lists. The latest Icarus Verilog and Verilator, as well as FPGA tools have full support for Verilog 2001 RTL. In my day job we are already experimenting with SystemVerilog. There is some progress in Icarus Verilog and Verilator, actually the biggest hindrance is Xilinx, which supports SystemVerilog only with Vivado, which is limited to series 7 devices, older devices will never be supported. Regards, Iztok Jeras On Wed, Apr 24, 2013 at 1:08 PM, Iztok Jeras <[email protected]> wrote: > Hi, > > On Wed, Apr 24, 2013 at 12:42 PM, Joel Holdsworth > <[email protected]> wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> On 24/04/13 11:34, Bert Vermeulen wrote: >>> On 04/23/2013 03:21 PM, Iztok Jeras wrote: >>>> Hi, >>>> >>>> I am offering my help for writing RTL, bench code in Verilog. I >>>> have experience writing code which is portable across various >>>> vendors (Altera, Xilinx, Lattice should also work). I should be >>>> able to read the Wiki on the weekend. As far as I was looking >>>> into various FPGA based logic analyzers, the main issue is not >>>> the FPGA code but the various devices used to interface to USB. I >>>> also have some spare FPGA boards, but not really logic analyzers >>>> specific board, so I am not sure if they fit. >>> >>> Iztok, >>> >>> That's great to hear. As a way to get started with a portable >>> source base, would porting the demon core be a good start? It's >>> what we have already, after all. > > I agree the demon core is a good start. I am already running: > svn2git http://gadgetforge.gadgetfactory.net/svn/butterflylogic > If there are no issues I will push it to Github, for now it seems slow > (already running for 8min). > >> >> Right now I would say yes, we should just adopt the demon core and >> start hacking on it. Does someone want to import the SVN repo? I can >> do it if noone else wants to - but only as far as github. >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v1.4.11 (GNU/Linux) >> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ >> >> iQEcBAEBAgAGBQJRd7b9AAoJEIsWlGmq62Igq3wIAJ2gHOgC5RzLTTRYyvTusLAg >> pZDO2zgdAg6HDmyZ8+btc+OyRB6U9KeSprxlFP4wOI4LOMSVzeaRvBANbQjIdY6M >> ftz+/OXEhdcuvj/HszR/jDMVmxDIipQfsqwPuN+kbK1GQOFcWwBErBRuj7m92ju4 >> X8MUdabee0ZbrvMkHaIDEUsUzLZ7uNEbUBelG5bXHa3haZ0Vu1bIWYByvuxMRLY1 >> WY/Qka5I53fHWpAplGQtP6GrslI7EFH5nH4vgVTYiPa4jDVBbHSJIXqLBbq/4vEF >> 6SeLlhm0lSeelh+CtNwdtO/airgyM8kqFJ4ED7xBF76eLJm1E77BS4JbUMrnHqw= >> =+7mk >> -----END PGP SIGNATURE----- >> >> ------------------------------------------------------------------------------ >> Try New Relic Now & We'll Send You this Cool Shirt >> New Relic is the only SaaS-based application performance monitoring service >> that delivers powerful full stack analytics. Optimize and monitor your >> browser, app, & servers with just a few lines of code. Try New Relic >> and get this awesome Nerd Life shirt! http://p.sf.net/sfu/newrelic_d2d_apr >> _______________________________________________ >> sigrok-devel mailing list >> [email protected] >> https://lists.sourceforge.net/lists/listinfo/sigrok-devel ------------------------------------------------------------------------------ Try New Relic Now & We'll Send You this Cool Shirt New Relic is the only SaaS-based application performance monitoring service that delivers powerful full stack analytics. Optimize and monitor your browser, app, & servers with just a few lines of code. Try New Relic and get this awesome Nerd Life shirt! http://p.sf.net/sfu/newrelic_d2d_apr _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
