When the start bit is not low at its sample point, then stop trying to interpret the remaining frame -- it's already known to be invalid, anyway.
Wait for the next start bit instead, assuming that either the falling edge which started the inspection of the UART frame and its start bit was a spurious glitch or that the captured signal does not communicate at the decoder's configured bitrate. Signed-off-by: Gerhard Sittig <[email protected]> --- decoders/uart/pd.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index e8e050105fc3..511a72cde8ba 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -223,11 +223,13 @@ def get_start_bit(self, rxtx, signal): self.startbit[rxtx] = signal - # The startbit must be 0. If not, we report an error. + # The startbit must be 0. If not, we report an error and wait + # for the next start bit (assuming this one was spurious). if self.startbit[rxtx] != 0: self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) - # TODO: Abort? Ignore rest of the frame? + self.state[rxtx] = 'WAIT FOR START BIT' + return self.cur_data_bit[rxtx] = 0 self.datavalue[rxtx] = 0 -- 1.9.1 ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
