On Sonntag, 9. August 2020 19:22:28 CEST David Slipper wrote: > Very interesting thread - nice to know that I'm not the only one to > think of it. > > Sadly, given the environment I work in, doing it that way would work but > be rather time consuming :-( > > My 16bit LA is based on the CY7C68013A module - and I note that there > are actually 3x 8bit channels available. > > Has anyone produced firmware that can pass up all 3 ?? (PA, PB, PD) I > realize that this would cut the bandwidth from 12MHz down to 8MHz (??) > but it might be of some interest.
Only Ports B and D are connected to the GPIF, PA could only be sampled by the main CPU. The Port A data would have to go a different USB endpoint buffer, it would not be interleaved with the data from the GPIF, so you won't get any advantage regarding alignment. Sampling by the main CPU would be significantly slower (reading from the GPIO data register, writing to the endpoint buffer, submitting the endpoint buffer to the SIE), I doubt you can do more than ~ 1MS/s with this approach. Kind regards, Stefan -- Stefan Brüns / Bergstraße 21 / 52062 Aachen phone: +49 241 53809034 mobile: +49 151 50412019
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