Hello,
I am currently working on NUCA cache implementation and I am new to
SimFlex. First of all, I would like to ask whether the complete list of
archive mails is the one found in the following links:
http://www.mail-archive.com/[email protected] (current)
http://www.mail-archive.com/[email protected] (old)
Or if I am missing anything.
I am trying to figure out how can I implement NUCA caches in SimFlex
4.0 (which will be built on Simics 4.0). That is, individual L2 cache
slices wired together and probably attached to different CPU cores.
I have searched in archive mails for similar questions and have only
found the following relevant threads:
* http://www.mail-archive.com/[email protected]/msg00243.html
* http://www.mail-archive.com/[email protected]/msg00247.html
Though they are based on SimFlex 3, and models in SimFlex 4 could be
different. I have read the available documentation
(http://parsa.epfl.ch/simflex/doc.html), though I haven't figured out
what models should I alter.
Moreover, I have been trying to find documentation for the L2 NUCA
caches that come with the Flexus codebase
(http://parsa.epfl.ch/simflex/software/Flexus-4.0.0.tar.gz), namely
flexus-4.0/simulators/CMP.L2SharedNUCA.Inorder and
flexus-4.0/simulators/CMP.L2SharedNUCA.OoO, but without success.
Thank you in advance and I am at your disposal for any further
information.
