Dear Chris, We have a tiled CMP model internally that supports both shared and private caches. Tiles communicate through an on-chip interconnect, and memory controllers participate in the interconnect as well. We plan to release the models sometime within the summer.
We'll post the new release announcement in the list and in our web site. Stay tuned! Regards, --nikos Nikos Hardavellas Carnegie Mellon - Computer Science Department 5000 Forbes Ave, Pittsburgh, PA 15213, USA +1 (412) 268-9611 ECE - Hamerschlag Hall A312 http://www.cs.cmu.edu/~hardav hardavellas at cmu.edu > -----Original Message----- > From: simflex-bounces at ece.cmu.edu [mailto:simflex-bounces at ece.cmu.edu] > On Behalf Of Chris Fensch > Sent: Thursday, May 21, 2009 6:32 AM > To: simflex at ece.cmu.edu > Subject: Re: [Simflex] Is there a Tiled CMP design? > > Hi, > > > tiled I mean each L2 bank is placed together with a core. The L2 is > shared > > and accesses to each bank are interleaved at cache line granularity. > > ups, forgot the most important bit: Each tile is connected by an on- > chip > packet-switched interconnect. > > Cheers > Chris > _______________________________________________ > SimFlex mailing list > SimFlex at ece.cmu.edu > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex
