Hello, I had a look a Flexus to model larger (32 cores and more) CMPs. One problem I found is that the CMP model uses a simple bus to connect the banked L2 cache to the cores. I don't think this kind of interconnect is scaleable. On the other side the DSM model assumes distributed cores with each core managing its own memory. Also it uses a protocol engine for home node assignment, etc. I think this adds unnecessary complexity to a CMP design.
As such, I would like to know, has anyone worked on a tiled CMP design? By tiled I mean each L2 bank is placed together with a core. The L2 is shared and accesses to each bank are interleaved at cache line granularity. Cheers Chris
