If there is no example & no documentation I would vote against it. It sounds too interesting but without both it's another extension that can't be used.
Knut Joel Sherrill schrieb: > Follow-up Comment #1, patch #6781 (project simulavr): > > Onno.. if I understand you correctly, this patch breaks nothing in an > existing simulation but simply improves the Verilog? Right? > > If so, does anyone see any reason not to apply this? _______________________________________________ Simulavr-devel mailing list [email protected] http://lists.nongnu.org/mailman/listinfo/simulavr-devel
