Knut Schwichtenberg wrote:
If there is no example & no documentation I would vote against it. It sounds too
interesting but without both it's another extension that can't be used.
The patch includes a new examples/verilog directory.
No changes to the manual.
What documentation someone needs for the Verilog interface
is beyond me. Onno can you add some to the manual?
Are there more objections?
--joel
Knut
Joel Sherrill schrieb:
Follow-up Comment #1, patch #6781 (project simulavr):
Onno.. if I understand you correctly, this patch breaks nothing in an
existing simulation but simply improves the Verilog? Right?
If so, does anyone see any reason not to apply this?
--
Joel Sherrill, Ph.D. Director of Research & Development
[email protected] On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
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