Hi Lev, Lev Serebryakov wrote: > Hello, Soren. > You wrote 1 апреля 2011 г., 4:06:29: > >> First configuration available will be 1Ghz/1Gbyte CPU Speed/Main Memory, >> later there will be probably 600Mhz/512Mbyte and 1.6Ghz/2Gbyte versions. >> Pricing have not be finalized yet, but should be attractive.... > Great work!
Thanks. > Please, please, give more information about ""24 pins header, > connected to user programable FPGA""! As I can see, here is > Lattice's FPGA on-board, am I right? How is it attached to main > board (bus, etc)? Could it access RAM or PCIe? Or only 24 pins > header? The user programble FPGA is a Xilinx XC3S50A, connected to the systems medium speed LPC bus. A custom option would also be a pin compatible XC2S200A. And before somebody ask "why not the PCIe bus", a PCIe bus is much more complex and would require minimum a 8 times as expensive FPGA and there are no free PCIe core. The LPC bus is very simple and there are plenty of code floating around, we will provide the basics. The Lattice FPGA is part of CPU control and power manangement. Best Regards, Soren Kristensen CEO & Chief Engineer Soekris Engineering, Inc. _______________________________________________ Soekris-tech mailing list [email protected] http://lists.soekris.com/mailman/listinfo/soekris-tech
