Module Name: src
Committed By: ryo
Date: Thu Oct 22 07:16:06 UTC 2020
Modified Files:
src/sys/arch/aarch64/aarch64: locore.S
Log Message:
Don't trap EL0 accesses to the DCC registers.
VMWare use "mrs xzr, mdccsr_el0" for guest side backdoor.
To generate a diff of this commit:
cvs rdiff -u -r1.73 -r1.74 src/sys/arch/aarch64/aarch64/locore.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/aarch64/aarch64/locore.S
diff -u src/sys/arch/aarch64/aarch64/locore.S:1.73 src/sys/arch/aarch64/aarch64/locore.S:1.74
--- src/sys/arch/aarch64/aarch64/locore.S:1.73 Tue Sep 15 09:28:20 2020
+++ src/sys/arch/aarch64/aarch64/locore.S Thu Oct 22 07:16:06 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $ */
+/* $NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -38,7 +38,7 @@
#include <aarch64/hypervisor.h>
#include "assym.h"
-RCSID("$NetBSD: locore.S,v 1.73 2020/09/15 09:28:20 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $")
#ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
#define MAIR_DEVICE_MEM MAIR_DEVICE_nGnRnE
@@ -241,9 +241,8 @@ ASEND(clear_bss)
init_sysregs:
stp x0, lr, [sp, #-16]!
- /* init debug event */
- ldr x0, mdscr_setting
- msr mdscr_el1, x0
+ /* init debug registers */
+ msr mdscr_el1, xzr
msr oslar_el1, xzr
/* Clear context id register */
@@ -1041,11 +1040,6 @@ sctlr_pac:
SCTLR_EnDB | /* PACDB (APDBKey_EL1) instruction enable */ \
0)
-mdscr_setting:
- .quad ( \
- MDSCR_TDCC | /* Trap Debug Communications Channel access */ \
- 0)
-
.L_devmap_addr:
.quad VM_KERNEL_IO_ADDRESS
