Module Name:    src
Committed By:   skrll
Date:           Thu Oct 22 07:31:15 UTC 2020

Modified Files:
        src/sys/arch/aarch64/aarch64: aarch64_machdep.c cpufunc.c db_machdep.c
            efi_machdep.c fpu.c pmap.c trap.c

Log Message:
Use the dmb/dsb/isb macros... if nothing else they're all now consistent
about the "memory" assembler contraint.

No binary change


To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53 src/sys/arch/aarch64/aarch64/aarch64_machdep.c
cvs rdiff -u -r1.25 -r1.26 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/aarch64/aarch64/db_machdep.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/aarch64/aarch64/efi_machdep.c
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/fpu.c
cvs rdiff -u -r1.91 -r1.92 src/sys/arch/aarch64/aarch64/pmap.c
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/aarch64/aarch64/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/aarch64/aarch64/aarch64_machdep.c
diff -u src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.52 src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.53
--- src/sys/arch/aarch64/aarch64/aarch64_machdep.c:1.52	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/aarch64_machdep.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.52 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.53 2020/10/22 07:31:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.52 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.53 2020/10/22 07:31:15 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_cpuoptions.h"
@@ -171,7 +171,7 @@ cpu_kernel_vm_init(uint64_t memory_start
 	/* Disable translation table walks using TTBR0 */
 	uint64_t tcr = reg_tcr_el1_read();
 	reg_tcr_el1_write(tcr | TCR_EPD0);
-	__asm __volatile("isb" ::: "memory");
+	isb();
 
 	aarch64_tlbi_all();
 

Index: src/sys/arch/aarch64/aarch64/cpufunc.c
diff -u src/sys/arch/aarch64/aarch64/cpufunc.c:1.25 src/sys/arch/aarch64/aarch64/cpufunc.c:1.26
--- src/sys/arch/aarch64/aarch64/cpufunc.c:1.25	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/cpufunc.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.c,v 1.25 2020/10/22 07:23:24 skrll Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -30,7 +30,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.25 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.26 2020/10/22 07:31:15 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -69,7 +69,7 @@ extract_cacheunit(int level, bool insn, 
 	/* select and extract level N data cache */
 	reg_csselr_el1_write(__SHIFTIN(level, CSSELR_LEVEL) |
 	    __SHIFTIN(insn ? 1 : 0, CSSELR_IND));
-	__asm __volatile ("isb");
+	isb();
 
 	ccsidr = reg_ccsidr_el1_read();
 	mmfr2 = reg_id_aa64mmfr2_el1_read();
@@ -391,10 +391,10 @@ aarch64_dcache_wbinv_all(void)
 		if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
 			break;
 
-		__asm __volatile ("dsb ish");
+		dsb(ish);
 		ln_dcache_wbinv_all(level, &cinfo[level].dcache);
 	}
-	__asm __volatile ("dsb ish");
+	dsb(ish);
 }
 
 void
@@ -409,10 +409,10 @@ aarch64_dcache_inv_all(void)
 		if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
 			break;
 
-		__asm __volatile ("dsb ish");
+		dsb(ish);
 		ln_dcache_inv_all(level, &cinfo[level].dcache);
 	}
-	__asm __volatile ("dsb ish");
+	dsb(ish);
 }
 
 void
@@ -427,10 +427,10 @@ aarch64_dcache_wb_all(void)
 		if (cinfo[level].cacheable == CACHE_CACHEABLE_NONE)
 			break;
 
-		__asm __volatile ("dsb ish");
+		dsb(ish);
 		ln_dcache_wb_all(level, &cinfo[level].dcache);
 	}
-	__asm __volatile ("dsb ish");
+	dsb(ish);
 }
 
 int

Index: src/sys/arch/aarch64/aarch64/db_machdep.c
diff -u src/sys/arch/aarch64/aarch64/db_machdep.c:1.27 src/sys/arch/aarch64/aarch64/db_machdep.c:1.28
--- src/sys/arch/aarch64/aarch64/db_machdep.c:1.27	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/db_machdep.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: db_machdep.c,v 1.27 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: db_machdep.c,v 1.28 2020/10/22 07:31:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.27 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: db_machdep.c,v 1.28 2020/10/22 07:31:15 skrll Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_compat_netbsd32.h"
@@ -444,13 +444,13 @@ db_md_pte_cmd(db_expr_t addr, bool have_
 	}
 
 	reg_s1e0r_write(addr);
-	__asm __volatile ("isb");
+	isb();
 	par = reg_par_el1_read();
 	db_printf("Stage1 EL0 translation %016llx -> PAR_EL1 = ", addr);
 	db_par_print(par, addr);
 
 	reg_s1e1r_write(addr);
-	__asm __volatile ("isb");
+	isb();
 	par = reg_par_el1_read();
 	db_printf("Stage1 EL1 translation %016llx -> PAR_EL1 = ", addr);
 	db_par_print(par, addr);

Index: src/sys/arch/aarch64/aarch64/efi_machdep.c
diff -u src/sys/arch/aarch64/aarch64/efi_machdep.c:1.7 src/sys/arch/aarch64/aarch64/efi_machdep.c:1.8
--- src/sys/arch/aarch64/aarch64/efi_machdep.c:1.7	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/efi_machdep.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: efi_machdep.c,v 1.7 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: efi_machdep.c,v 1.8 2020/10/22 07:31:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.7 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: efi_machdep.c,v 1.8 2020/10/22 07:31:15 skrll Exp $");
 
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
@@ -91,7 +91,7 @@ arm_efirt_md_enter(void)
 
 	/* Enable FP access (AArch64 UEFI calling convention) */
 	reg_cpacr_el1_write(CPACR_FPEN_ALL);
-	__asm __volatile ("isb");
+	isb();
 
 	/*
 	 * Install custom fault handler. EFI lock is held across calls so
@@ -107,7 +107,7 @@ arm_efirt_md_exit(void)
 
 	/* Disable FP access */
 	reg_cpacr_el1_write(CPACR_FPEN_NONE);
-	__asm __volatile ("isb");
+	isb();
 
 	/* Restore FPU state */
 	if (arm_efirt_state.fpu_used)

Index: src/sys/arch/aarch64/aarch64/fpu.c
diff -u src/sys/arch/aarch64/aarch64/fpu.c:1.9 src/sys/arch/aarch64/aarch64/fpu.c:1.10
--- src/sys/arch/aarch64/aarch64/fpu.c:1.9	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/fpu.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu.c,v 1.9 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: fpu.c,v 1.10 2020/10/22 07:31:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.9 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: fpu.c,v 1.10 2020/10/22 07:31:15 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -146,7 +146,7 @@ fpu_state_load(lwp_t *l, unsigned int fl
 	/* allow user process to use FP */
 	l->l_md.md_cpacr = CPACR_FPEN_ALL;
 	reg_cpacr_el1_write(CPACR_FPEN_ALL);
-	__asm __volatile ("isb");
+	isb();
 
 	if ((flags & PCU_REENABLE) == 0)
 		load_fpregs(&pcb->pcb_fpregs);
@@ -160,12 +160,12 @@ fpu_state_save(lwp_t *l)
 	curcpu()->ci_vfp_save.ev_count++;
 
 	reg_cpacr_el1_write(CPACR_FPEN_EL1);	/* fpreg access enable */
-	__asm __volatile ("isb");
+	isb();
 
 	save_fpregs(&pcb->pcb_fpregs);
 
 	reg_cpacr_el1_write(CPACR_FPEN_NONE);	/* fpreg access disable */
-	__asm __volatile ("isb");
+	isb();
 }
 
 static void
@@ -176,7 +176,7 @@ fpu_state_release(lwp_t *l)
 	/* disallow user process to use FP */
 	l->l_md.md_cpacr = CPACR_FPEN_NONE;
 	reg_cpacr_el1_write(CPACR_FPEN_NONE);
-	__asm __volatile ("isb");
+	isb();
 }
 
 static const struct fpreg zero_fpreg;
@@ -224,7 +224,7 @@ fpu_kern_enter(void)
 	 * executing any further instructions.
 	 */
 	reg_cpacr_el1_write(CPACR_FPEN_ALL);
-	arm_isb();
+	isb();
 }
 
 void
@@ -255,7 +255,7 @@ fpu_kern_leave(void)
 	 * it again.
 	 */
 	reg_cpacr_el1_write(CPACR_FPEN_NONE);
-	arm_isb();
+	isb();
 
 	s = ci->ci_kfpu_spl;
 	ci->ci_kfpu_spl = -1;

Index: src/sys/arch/aarch64/aarch64/pmap.c
diff -u src/sys/arch/aarch64/aarch64/pmap.c:1.91 src/sys/arch/aarch64/aarch64/pmap.c:1.92
--- src/sys/arch/aarch64/aarch64/pmap.c:1.91	Mon Sep 28 12:04:19 2020
+++ src/sys/arch/aarch64/aarch64/pmap.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.c,v 1.91 2020/09/28 12:04:19 skrll Exp $	*/
+/*	$NetBSD: pmap.c,v 1.92 2020/10/22 07:31:15 skrll Exp $	*/
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <r...@nerv.org>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.91 2020/09/28 12:04:19 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.92 2020/10/22 07:31:15 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -46,6 +46,8 @@ __KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.9
 #include <uvm/uvm.h>
 #include <uvm/pmap/pmap_pvt.h>
 
+#include <arm/cpufunc.h>
+
 #include <aarch64/pmap.h>
 #include <aarch64/pte.h>
 #include <aarch64/armreg.h>
@@ -793,7 +795,7 @@ pmap_extract_coherency(struct pmap *pm, 
 			 */
 			register_t s = daif_disable(DAIF_I|DAIF_F);
 			reg_s1e1r_write(va);
-			__asm __volatile ("isb");
+			isb();
 			uint64_t par = reg_par_el1_read();
 			reg_daif_write(s);
 
@@ -1440,7 +1442,7 @@ pmap_activate(struct lwp *l)
 	/* Disable translation table walks using TTBR0 */
 	tcr = reg_tcr_el1_read();
 	reg_tcr_el1_write(tcr | TCR_EPD0);
-	__asm __volatile("isb" ::: "memory");
+	isb();
 
 	/* XXX: allocate asid, and regenerate if needed */
 	if (pm->pm_asid == -1)
@@ -1452,7 +1454,7 @@ pmap_activate(struct lwp *l)
 	/* Re-enable translation table walks using TTBR0 */
 	tcr = reg_tcr_el1_read();
 	reg_tcr_el1_write(tcr & ~TCR_EPD0);
-	__asm __volatile("isb" ::: "memory");
+	isb();
 
 	pm->pm_activated = true;
 

Index: src/sys/arch/aarch64/aarch64/trap.c
diff -u src/sys/arch/aarch64/aarch64/trap.c:1.39 src/sys/arch/aarch64/aarch64/trap.c:1.40
--- src/sys/arch/aarch64/aarch64/trap.c:1.39	Thu Oct 22 07:23:24 2020
+++ src/sys/arch/aarch64/aarch64/trap.c	Thu Oct 22 07:31:15 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.39 2020/10/22 07:23:24 skrll Exp $ */
+/* $NetBSD: trap.c,v 1.40 2020/10/22 07:31:15 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.39 2020/10/22 07:23:24 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: trap.c,v 1.40 2020/10/22 07:31:15 skrll Exp $");
 
 #include "opt_arm_intr_impl.h"
 #include "opt_compat_netbsd32.h"
@@ -717,7 +717,7 @@ emul_arm_insn(struct trapframe *tf)
 			 * mcr p15, 0, <Rd>, c7, c5, 4
 			 * (flush prefetch buffer)
 			 */
-			__asm __volatile("isb sy" ::: "memory");
+			isb();
 		}
 		goto emulated;
 	case 0x0e070f9a:
@@ -726,7 +726,7 @@ emul_arm_insn(struct trapframe *tf)
 			 * mcr p15, 0, <Rd>, c7, c10, 4
 			 * (data synchronization barrier)
 			 */
-			__asm __volatile("dsb sy" ::: "memory");
+			dsb(sy);
 		}
 		goto emulated;
 	case 0x0e070fba:
@@ -735,7 +735,7 @@ emul_arm_insn(struct trapframe *tf)
 			 * mcr p15, 0, <Rd>, c7, c10, 5
 			 * (data memory barrier)
 			 */
-			__asm __volatile("dmb sy" ::: "memory");
+			dmb(sy);
 		}
 		goto emulated;
 	default:

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