Module Name: src
Committed By: skrll
Date: Sun Nov 1 21:09:48 UTC 2020
Modified Files:
src/sys/arch/riscv/include: sysreg.h
src/sys/arch/riscv/riscv: trap.c
Log Message:
Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.5 src/sys/arch/riscv/include/sysreg.h:1.6
--- src/sys/arch/riscv/include/sysreg.h:1.5 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/sysreg.h Sun Nov 1 21:09:48 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.6 2020/11/01 21:09:48 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -155,18 +155,24 @@ riscvreg_status_set(uint32_t __mask)
}
// Cause register
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
+#define CAUSE_FETCH_MISALIGNED 0
+#define CAUSE_FETCH_ACCESS 1
#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_MISALIGNED_LOAD 4
-#define CAUSE_FAULT_LOAD 5
-#define CAUSE_MISALIGNED_STORE 6
-#define CAUSE_FAULT_STORE 7
+#define CAUSE_BREAKPOINT 3
+#define CAUSE_LOAD_MISALIGNED 4
+#define CAUSE_LOAD_ACCESS 5
+#define CAUSE_STORE_MISALIGNED 6
+#define CAUSE_STORE_ACCESS 7
#define CAUSE_SYSCALL 8
-#define CAUSE_BREAKPOINT 9
-#define CAUSE_FP_DISABLED 10
-#define CAUSE_ACCELERATOR_DISABLED 12
+#define CAUSE_USER_ECALL 8
+#define CAUSE_SUPERVISOR_ECALL 9
+/* 10 is reserved */
+#define CAUSE_MACHINE_ECALL 11
+#define CAUSE_FETCH_PAGE_FAULT 12
+#define CAUSE_LOAD_PAGE_FAULT 13
+/* 14 is Reserved */
+#define CAUSE_STORE_PAGE_FAULT 15
+/* >= 16 is reserved */
static inline uint64_t
riscvreg_cycle_read(void)
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.9 src/sys/arch/riscv/riscv/trap.c:1.10
--- src/sys/arch/riscv/riscv/trap.c:1.9 Sun Nov 1 21:06:22 2020
+++ src/sys/arch/riscv/riscv/trap.c Sun Nov 1 21:09:48 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.9 2020/11/01 21:06:22 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.10 2020/11/01 21:09:48 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -46,27 +46,24 @@ __RCSID("$NetBSD: trap.c,v 1.9 2020/11/0
#include <riscv/locore.h>
-#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_PRIVILEGED_INSTRUCTION) \
- |__BIT(CAUSE_ILLEGAL_INSTRUCTION))
+#define INSTRUCTION_TRAP_MASK (__BIT(CAUSE_ILLEGAL_INSTRUCTION))
-#define FAULT_TRAP_MASK (__BIT(CAUSE_FAULT_FETCH) \
- |__BIT(CAUSE_FAULT_LOAD) \
- |__BIT(CAUSE_FAULT_STORE))
-
-#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_MISALIGNED_FETCH) \
- |__BIT(CAUSE_MISALIGNED_LOAD) \
- |__BIT(CAUSE_MISALIGNED_STORE))
+#define FAULT_TRAP_MASK (__BIT(CAUSE_FETCH_ACCESS) \
+ |__BIT(CAUSE_LOAD_ACCESS) \
+ |__BIT(CAUSE_STORE_ACCESS))
+
+#define MISALIGNED_TRAP_MASK (__BIT(CAUSE_FETCH_MISALIGNED) \
+ |__BIT(CAUSE_LOAD_MISALIGNED) \
+ |__BIT(CAUSE_STORE_MISALIGNED))
static const char * const causenames[] = {
- [CAUSE_MISALIGNED_FETCH] = "misaligned fetch",
- [CAUSE_MISALIGNED_LOAD] = "misaligned load",
- [CAUSE_MISALIGNED_STORE] = "misaligned store",
- [CAUSE_FAULT_FETCH] = "fetch",
- [CAUSE_FAULT_LOAD] = "load",
- [CAUSE_FAULT_STORE] = "store",
- [CAUSE_FP_DISABLED] = "fp disabled",
+ [CAUSE_FETCH_MISALIGNED] = "misaligned fetch",
+ [CAUSE_LOAD_MISALIGNED] = "misaligned load",
+ [CAUSE_STORE_MISALIGNED] = "misaligned store",
+ [CAUSE_FETCH_ACCESS] = "fetch",
+ [CAUSE_LOAD_ACCESS] = "load",
+ [CAUSE_STORE_ACCESS] = "store",
[CAUSE_ILLEGAL_INSTRUCTION] = "illegal instruction",
- [CAUSE_PRIVILEGED_INSTRUCTION] = "privileged instruction",
[CAUSE_BREAKPOINT] = "breakpoint",
};
@@ -220,11 +217,11 @@ cpu_trapsignal(struct trapframe *tf, ksi
static inline vm_prot_t
get_faulttype(register_t cause)
{
- if (cause == CAUSE_FAULT_LOAD)
+ if (cause == CAUSE_LOAD_ACCESS)
return VM_PROT_READ;
- if (cause == CAUSE_FAULT_STORE)
+ if (cause == CAUSE_STORE_ACCESS)
return VM_PROT_READ | VM_PROT_WRITE;
- KASSERT(cause == CAUSE_FAULT_FETCH);
+ KASSERT(cause == CAUSE_FETCH_ACCESS);
return VM_PROT_READ | VM_PROT_EXECUTE;
}
@@ -256,12 +253,12 @@ trap_pagefault_fixup(struct trapframe *t
attr |= VM_PAGEMD_REFERENCED;
}
#if 0 /* XXX Outdated */
- if (cause == CAUSE_FAULT_STORE) {
+ if (cause == CAUSE_STORE_ACCESS) {
if ((npte & PTE_NW) != 0) {
npte &= ~PTE_NW;
attr |= VM_PAGEMD_MODIFIED;
}
- } else if (cause == CAUSE_FAULT_FETCH) {
+ } else if (cause == CAUSE_FETCH_ACCESS) {
if ((npte & PTE_NX) != 0) {
npte &= ~PTE_NX;
attr |= VM_PAGEMD_EXECPAGE;
@@ -349,9 +346,8 @@ static bool
trap_instruction(struct trapframe *tf, register_t epc, register_t status,
register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
{
- const bool prvopc_p = (cause == CAUSE_PRIVILEGED_INSTRUCTION);
if (usertrap_p) {
- trap_ksi_init(ksi, SIGILL, prvopc_p ? ILL_PRVOPC : ILL_ILLOPC,
+ trap_ksi_init(ksi, SIGILL, ILL_ILLOPC,
(intptr_t)badaddr, cause);
}
return false;
@@ -395,12 +391,14 @@ cpu_trap(struct trapframe *tf, register_
} else if (fault_mask & INSTRUCTION_TRAP_MASK) {
ok = trap_instruction(tf, epc, status, cause, addr,
usertrap_p, &ksi);
+#if 0
} else if (fault_mask && __BIT(CAUSE_FP_DISABLED)) {
if (!usertrap_p) {
panic("%s: fp used @ %#"PRIxREGISTER" in kernel!",
__func__, tf->tf_pc);
}
fpu_load();
+#endif
} else if (fault_mask & MISALIGNED_TRAP_MASK) {
ok = trap_misalignment(tf, epc, status, cause, addr,
usertrap_p, &ksi);
