Module Name: src
Committed By: skrll
Date: Wed Nov 4 06:56:56 UTC 2020
Modified Files:
src/sys/arch/riscv/conf: GENERIC files.riscv
src/sys/arch/riscv/include: frame.h locore.h sysreg.h
src/sys/arch/riscv/riscv: core_machdep.c db_machdep.c genassym.cf
locore.S trap.c
Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf
Some from zmcgrew@
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/conf/GENERIC
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/riscv/conf/files.riscv
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/riscv/include/frame.h
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/riscv/include/locore.h
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/riscv/riscv/core_machdep.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/riscv/riscv/db_machdep.c
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/riscv/riscv/genassym.cf
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/riscv/riscv/trap.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/riscv/conf/GENERIC
diff -u src/sys/arch/riscv/conf/GENERIC:1.10 src/sys/arch/riscv/conf/GENERIC:1.11
--- src/sys/arch/riscv/conf/GENERIC:1.10 Sat Jun 1 12:42:27 2019
+++ src/sys/arch/riscv/conf/GENERIC Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.10 2019/06/01 12:42:27 maxv Exp $
+# $NetBSD: GENERIC,v 1.11 2020/11/04 06:56:56 skrll Exp $
#
# GENERIC machine description file
#
@@ -22,12 +22,12 @@ include "arch/riscv/conf/std.riscv64"
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.10 $"
+#ident "GENERIC-$Revision: 1.11 $"
maxusers 64 # estimated number of users
# Standard system options
-
+#options FPE # Floating-point extension support
options NTP # NTP phase/frequency locked loop
options KTRACE # system call tracing via ktrace(1)
Index: src/sys/arch/riscv/conf/files.riscv
diff -u src/sys/arch/riscv/conf/files.riscv:1.6 src/sys/arch/riscv/conf/files.riscv:1.7
--- src/sys/arch/riscv/conf/files.riscv:1.6 Wed Oct 21 13:31:51 2020
+++ src/sys/arch/riscv/conf/files.riscv Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-# $NetBSD: files.riscv,v 1.6 2020/10/21 13:31:51 christos Exp $
+# $NetBSD: files.riscv,v 1.7 2020/11/04 06:56:56 skrll Exp $
#
maxpartitions 16
@@ -14,7 +14,7 @@ file arch/riscv/riscv/cpu_subr.c
file arch/riscv/riscv/db_disasm.c ddb
file arch/riscv/riscv/db_trace.c ddb
file arch/riscv/riscv/fixup.c
-file arch/riscv/riscv/fpu.c
+file arch/riscv/riscv/fpu.c fpe
file arch/riscv/riscv/ipifuncs.c multiprocessor
file arch/riscv/riscv/stubs.c
file arch/riscv/riscv/syscall.c # syscall handler
Index: src/sys/arch/riscv/include/frame.h
diff -u src/sys/arch/riscv/include/frame.h:1.2 src/sys/arch/riscv/include/frame.h:1.3
--- src/sys/arch/riscv/include/frame.h:1.2 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/frame.h Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: frame.h,v 1.2 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: frame.h,v 1.3 2020/11/04 06:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,10 +36,10 @@
struct trapframe {
struct reg tf_regs __aligned(8);
- register_t tf_badvaddr;
- register_t tf_pc;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register_t tf_stval; // supervisor trap value
+ register_t tf_sepc; // supervisor exception program counter
+ register_t tf_scause; // supervisor cause register
+ register_t tf_sr; // supervisor status register
#define tf_reg tf_regs.r_reg
#define tf_a0 tf_reg[_X_A0]
#define tf_t0 tf_reg[_X_T0]
Index: src/sys/arch/riscv/include/locore.h
diff -u src/sys/arch/riscv/include/locore.h:1.5 src/sys/arch/riscv/include/locore.h:1.6
--- src/sys/arch/riscv/include/locore.h:1.5 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/include/locore.h Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.5 2020/03/14 16:12:16 skrll Exp $ */
+/* $NetBSD: locore.h,v 1.6 2020/11/04 06:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -39,9 +39,9 @@
struct trapframe {
struct reg tf_regs;
- register_t tf_badaddr;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register_t tf_tval;
+ register_t tf_cause;
+ register_t tf_sr;
#define tf_reg tf_regs.r_reg
#define tf_pc tf_regs.r_pc
#define tf_ra tf_reg[_X_RA]
@@ -80,9 +80,9 @@ struct trapframe {
// For COMPAT_NETBSD32 coredumps
struct trapframe32 {
struct reg32 tf_regs;
- register32_t tf_badaddr;
- uint32_t tf_cause; // 32-bit register
- uint32_t tf_sr; // 32-bit register
+ register32_t tf_tval;
+ register32_t tf_cause;
+ register32_t tf_sr;
};
#define FB_A0 0
@@ -105,7 +105,7 @@ struct trapframe32 {
struct faultbuf {
register_t fb_reg[FB_MAX];
- uint32_t fb_sr;
+ register_t fb_sr;
};
CTASSERT(sizeof(label_t) == sizeof(struct faultbuf));
Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.8 src/sys/arch/riscv/include/sysreg.h:1.9
--- src/sys/arch/riscv/include/sysreg.h:1.8 Mon Nov 2 08:37:59 2020
+++ src/sys/arch/riscv/include/sysreg.h Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.8 2020/11/02 08:37:59 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.9 2020/11/04 06:56:56 skrll Exp $ */
/*
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -43,6 +43,7 @@
#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
+#define FCSR_FRM_DYN 0b111 // Dynamic rounding
#define FCSR_FFLAGS __BITS(4,0) // Sticky bits
#define FCSR_NV __BIT(4) // iNValid operation
#define FCSR_DZ __BIT(3) // Divide by Zero
@@ -101,25 +102,77 @@ riscvreg_fcsr_write_frm(uint32_t __new)
return __SHIFTOUT(__old, FCSR_FRM);
}
-// Status Register
-#define SR_IP __BITS(31,24) // Pending interrupts
-#define SR_IM __BITS(23,16) // Interrupt Mask
-#define SR_VM __BIT(7) // MMU On
-#define SR_S64 __BIT(6) // RV64 supervisor mode
-#define SR_U64 __BIT(5) // RV64 user mode
-#define SR_EF __BIT(4) // Enable Floating Point
-#define SR_PEI __BIT(3) // Previous EI setting
-#define SR_EI __BIT(2) // Enable interrupts
-#define SR_PS __BIT(1) // Previous (S) supervisor setting
-#define SR_S __BIT(0) // Supervisor
+/* Supervisor Status Register */
+#ifdef _LP64
+#define SR_WPRI __BITS(62, 34) | __BITS(31,20) | __BIT(17) | \
+ __BITS(12,9) | __BITS(7,6) | __BITS(3,2)
+#define SR_SD __BIT(63)
+ /* Bits 62-34 are WPRI */
+#define SR_UXL __BITS(33,32)
+#define SR_UXL_32 1
+#define SR_UXL_64 2
+#define SR_UXL_128 3
+ /* Bits 31-20 are WPRI*/
+#else
+#define SR_WPRI __BITS(30,20) | __BIT(17) | __BITS(12,9) | \
+ __BITS(7,6) | __BITS(3,2)
+#define SR_SD __BIT(31)
+ /* Bits 30-20 are WPRI*/
+#endif /* _LP64 */
+
+/* Both RV32 and RV64 have the bottom 20 bits shared */
+#define SR_MXR __BIT(19)
+#define SR_SUM __BIT(18)
+ /* Bit 17 is WPRI */
+#define SR_XS __BITS(16,15)
+#define SR_FS __BITS(14,13)
+#define SR_FS_OFF 0
+#define SR_FS_INITIAL 1
+#define SR_FS_CLEAN 2
+#define SR_FS_DIRTY 3
+
+ /* Bits 12-9 are WPRI */
+#define SR_SPP __BIT(8)
+ /* Bits 7-6 are WPRI */
+#define SR_SPIE __BIT(5)
+#define SR_UPIE __BIT(4)
+ /* Bits 3-2 are WPRI */
+#define SR_SIE __BIT(1)
+#define SR_UIE __BIT(0)
+
+/* Supervisor interrupt registers */
+/* ... interupt pending register (sip) */
+ /* Bit (XLEN-1)-10 is WIRI */
+#define SIP_SEIP __BIT(9)
+#define SIP_UEIP __BIT(8)
+ /* Bit 7-6 is WIRI */
+#define SIP_STIP __BIT(5)
+#define SIP_UTIP __BIT(4)
+ /* Bit 3-2 is WIRI */
+#define SIP_SSIP __BIT(1)
+#define SIP_USIP __BIT(0)
+
+/* ... interupt-enable register (sie) */
+ /* Bit (XLEN-1) - 10 is WIRI */
+#define SIE_SEIE __BIT(9)
+#define SIE_UEIE __BIT(8)
+ /* Bit 7-6 is WIRI */
+#define SIE_STIE __BIT(5)
+#define SIE_UTIE __BIT(4)
+ /* Bit 3-2 is WIRI */
+#define SIE_SSIE __BIT(1)
+#define SIE_USIE __BIT(0)
+
+/* Mask for all interrupts */
+#define SIE_IM (SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
#ifdef _LP64
-#define SR_USER (SR_EI|SR_U64|SR_S64|SR_VM|SR_IM)
+#define SR_USER (SR_UIE | SR_U64 | SR_S64 | SR_IM)
#define SR_USER32 (SR_USER & ~SR_U64)
-#define SR_KERNEL (SR_S|SR_EI|SR_U64|SR_S64|SR_VM)
+#define SR_KERNEL (SR_S | SR_UIE | SR_U64 | SR_S64)
#else
-#define SR_USER (SR_EI|SR_VM|SR_IM)
-#define SR_KERNEL (SR_S|SR_EI|SR_VM)
+#define SR_USER (SR_UIE||SR_IM)
+#define SR_KERNEL (SR_S|SR_UIE)
#endif
static inline uint32_t
Index: src/sys/arch/riscv/riscv/core_machdep.c
diff -u src/sys/arch/riscv/riscv/core_machdep.c:1.3 src/sys/arch/riscv/riscv/core_machdep.c:1.4
--- src/sys/arch/riscv/riscv/core_machdep.c:1.3 Wed Nov 20 19:37:52 2019
+++ src/sys/arch/riscv/riscv/core_machdep.c Wed Nov 4 06:56:56 2020
@@ -30,7 +30,7 @@
#include <sys/cdefs.h>
#ifndef CORENAME
-__RCSID("$NetBSD: core_machdep.c,v 1.3 2019/11/20 19:37:52 pgoyette Exp $");
+__RCSID("$NetBSD: core_machdep.c,v 1.4 2020/11/04 06:56:56 skrll Exp $");
#endif
#include <sys/param.h>
@@ -81,7 +81,7 @@ CORENAME(cpu_coredump)(struct lwp *l, st
cpustate.tf.tf_reg[i] = tf->tf_reg[i];
}
cpustate.tf.tf_pc = tf->tf_pc;
- cpustate.tf.tf_badaddr = tf->tf_badaddr;
+ cpustate.tf.tf_tval = tf->tf_tval;
cpustate.tf.tf_cause = tf->tf_cause;
cpustate.tf.tf_sr = tf->tf_sr;
if (fpu_valid_p(l)) {
Index: src/sys/arch/riscv/riscv/db_machdep.c
diff -u src/sys/arch/riscv/riscv/db_machdep.c:1.4 src/sys/arch/riscv/riscv/db_machdep.c:1.5
--- src/sys/arch/riscv/riscv/db_machdep.c:1.4 Sat Mar 14 16:12:16 2020
+++ src/sys/arch/riscv/riscv/db_machdep.c Wed Nov 4 06:56:56 2020
@@ -29,7 +29,7 @@
#include <sys/cdefs.h>
-__RCSID("$NetBSD: db_machdep.c,v 1.4 2020/03/14 16:12:16 skrll Exp $");
+__RCSID("$NetBSD: db_machdep.c,v 1.5 2020/11/04 06:56:56 skrll Exp $");
#include <sys/param.h>
@@ -80,7 +80,7 @@ const struct db_variable db_regs[] = {
{ "pc", (void *)offsetof(struct trapframe, tf_pc), db_rw_ddbreg, NULL },
{ "status", (void *)offsetof(struct trapframe, tf_sr), db_rw_ddbreg, "i" },
{ "cause", (void *)offsetof(struct trapframe, tf_cause), db_rw_ddbreg, "i" },
- { "badaddr", (void *)offsetof(struct trapframe, tf_badaddr), db_rw_ddbreg, NULL },
+ { "tval", (void *)offsetof(struct trapframe, tf_tval), db_rw_ddbreg, NULL },
};
const struct db_variable * const db_eregs = db_regs + __arraycount(db_regs);
Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.7 src/sys/arch/riscv/riscv/genassym.cf:1.8
--- src/sys/arch/riscv/riscv/genassym.cf:1.7 Wed Jan 8 17:38:42 2020
+++ src/sys/arch/riscv/riscv/genassym.cf Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.7 2020/01/08 17:38:42 ad Exp $
+# $NetBSD: genassym.cf,v 1.8 2020/11/04 06:56:56 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
# All rights reserved.
@@ -47,17 +47,18 @@ include <uvm/uvm_extern.h>
include <riscv/locore.h>
include <riscv/sysreg.h>
-define SR_IM SR_IM
-define SR_IM_LSHIFT __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
-define SR_IM_RSHIFT ilog2(__LOWEST_SET_BIT(SR_IM))
-define SR_VM SR_VM
-define SR_U64 SR_U64
-define SR_S64 SR_S64
-define SR_EF SR_EF
-define SR_PEI SR_PEI
-define SR_EI SR_EI
-define SR_PS SR_PS
-define SR_S SR_S
+#define SR_IM SR_IM
+#define SR_IM_LSHIFT __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
+#define SR_IM_RSHIFT ilog2(__LOWEST_SET_BIT(SR_IM))
+#define SR_VM SR_VM
+#define SR_U64 SR_U64
+#define SR_S64 SR_S64
+#define SR_EF SR_EF
+#define SR_PEI SR_PEI
+#define SR_EI SR_EI
+#define SR_PS SR_PS
+#define SR_S SR_S
+define SR_SIE SR_SIE
define CAUSE_SYSCALL CAUSE_SYSCALL
@@ -106,8 +107,8 @@ define TF_T5 offsetof(struct trapframe,
define TF_T6 offsetof(struct trapframe, tf_reg[_X_T6])
define TF_GP offsetof(struct trapframe, tf_reg[_X_GP])
define TF_PC offsetof(struct trapframe, tf_pc)
-define TF_CAUSE offsetof(struct trapframe, tf_cause)
-define TF_BADADDR offsetof(struct trapframe, tf_badaddr)
+define TF_SCAUSE offsetof(struct trapframe, tf_scause)
+define TF_STVAL offsetof(struct trapframe, tf_stval)
define TF_SR offsetof(struct trapframe, tf_sr)
define L_CPU offsetof(struct lwp, l_cpu)
Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.13 src/sys/arch/riscv/riscv/locore.S:1.14
--- src/sys/arch/riscv/riscv/locore.S:1.13 Sat Oct 31 15:18:09 2020
+++ src/sys/arch/riscv/riscv/locore.S Wed Nov 4 06:56:56 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.13 2020/10/31 15:18:09 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.14 2020/11/04 06:56:56 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -40,10 +40,10 @@ ENTRY_NP(start)
#ifdef _LP64
li t0, SR_U64|SR_S64
- li t1, SR_IM|SR_VM|SR_EI
+ li t1, SR_IM|SR_SIE
csrs sstatus, t0
#else
- li t1, SR_IM|SR_VM|SR_U64|SR_S64|R_EI
+ li t1, SR_IM|SR_U64|SR_S64|SR_EI
#endif
csrc sstatus, t1
@@ -127,10 +127,6 @@ ENTRY_NP(start)
bgtz a6, .Lfill // loop if more
#endif
- csrw sptbr, s1 // set the page table base
- li t0, SR_VM
- csrs sstatus, t0 // Enable VM
-
// We should have a VM so let's start using our real addresses
lui t0, %hi(.Lmmu_on) // load hi part of absolute address
jr t0, %lo(.Lmmu_on) // jump to absolute address
@@ -185,7 +181,7 @@ ENTRY_NP(cpu_switchto)
REG_S sp, L_MD_KTF(a0) // record trapframe pointer
- csrrci t0, sstatus, SR_EI // # disable interrupts
+ csrrci t0, sstatus, SR_SIE // # disable interrupts
mv tp, a1 // # put the new lwp in thread pointer
@@ -274,28 +270,20 @@ ENTRY_NP(cpu_fast_switchto)
mv s0, tp // remember curlwp
mv s1, sp // remember kernel stack
-#if 0
- csrrci t0, sstatus, SR_EI // disable interrupts
-#endif
+ csrrci t0, sstatus, SR_SIE // disable interrupts
PTR_L t1, L_CPU(tp) // get curcpu()
PTR_S sp, L_MD_KTF(tp) // save trapframe ptr in oldlwp
mv tp, a0 // set thread pointer to newlwp
PTR_S tp, CI_CURLWP(t1) // update curlwp
PTR_L sp, L_MD_KTF(tp) // switch to its stack
-#if 0
csrw sstatus, t0 // reenable interrupts
-#endif
call _C_LABEL(softint_dispatch)
-#if 0
- csrrci t0, sstatus, SR_EI // disable interrupts
-#endif
+ csrrci t0, sstatus, SR_SIE // disable interrupts
PTR_L t1, L_CPU(tp) // get curcpu() again
mv tp, s0 // return to pinned lwp
PTR_S tp, CI_CURLWP(t1) // restore curlwp
-#if 0
csrw sstatus, t0 // reeanble interrupts
-#endif
mv sp, s1 // restore stack pointer
REG_L ra, (TF_RA + CALLFRAME_RA)(sp) // get return address
@@ -378,9 +366,9 @@ ENTRY_NP(cpu_exception_handler)
bltz a3, intr_handler // MSB is set if interrupt
- // badaddr is only relavent for non-interrupts
- csrr a4, sbadaddr // get badaddr
- REG_S a4, TF_BADADDR(sp)
+ // stval is only relavent for non-interrupts
+ csrr a4, stval // get stval
+ REG_S a4, TF_TVAL(sp)
beqz t1, trap_user // this was a user trap
// This was a kernel exception
@@ -390,7 +378,7 @@ exception_kernexit:
// trap or interrupt). Simply return the volatile registers and the
// exception PC and status, load the saved SP from the trapframe, and
// return from the exception
- csrrci zero, sstatus, SR_EI // disable interrupts
+ csrrci zero, sstatus, SR_SIE // disable interrupts
REG_L ra, TF_RA(sp) // restore return address
REG_L gp, TF_GP(sp) // restore gp
@@ -433,7 +421,7 @@ trap_user:
REG_S s10, TF_S10(sp) // only save from userland
REG_S s11, TF_S11(sp) // only save from userland
- csrsi sstatus, SR_EI // reenable interrupts
+ csrsi sstatus, SR_SIE // reenable interrupts
li t0, CAUSE_SYSCALL // let's see if this was a syscall
beq a3, t0, trap_syscall // yes it was
@@ -442,7 +430,7 @@ trap_user:
_C_LABEL(exception_userexit):
INT_L t0, L_MD_ASTPENDING(tp) // ast pending?
bnez t0, trap_doast // yes, handle it.
- csrrci zero, sstatus, SR_EI // disable interrupts
+ csrrci zero, sstatus, SR_SIE // disable interrupts
csrw sscratch, tp // show we are coming from userland
REG_L tp, TF_TP(sp) // only restore from userland
REG_L s0, TF_S0(sp) // only restore from userland
Index: src/sys/arch/riscv/riscv/trap.c
diff -u src/sys/arch/riscv/riscv/trap.c:1.10 src/sys/arch/riscv/riscv/trap.c:1.11
--- src/sys/arch/riscv/riscv/trap.c:1.10 Sun Nov 1 21:09:48 2020
+++ src/sys/arch/riscv/riscv/trap.c Wed Nov 4 06:56:56 2020
@@ -32,7 +32,7 @@
#define __PMAP_PRIVATE
#define __UFETCHSTORE_PRIVATE
-__RCSID("$NetBSD: trap.c,v 1.10 2020/11/01 21:09:48 skrll Exp $");
+__RCSID("$NetBSD: trap.c,v 1.11 2020/11/04 06:56:56 skrll Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -167,7 +167,7 @@ dump_trapframe(const struct trapframe *t
(*pr)("Trapframe @ %p "
"(cause=%d (%s), status=%#x, pc=%#16"PRIxREGISTER
", va=%#"PRIxREGISTER"):\n",
- tf, tf->tf_cause, causestr, tf->tf_sr, tf->tf_pc, tf->tf_badaddr);
+ tf, tf->tf_cause, causestr, tf->tf_sr, tf->tf_pc, tf->tf_tval);
(*pr)("ra=%#16"PRIxREGISTER", sp=%#16"PRIxREGISTER
", gp=%#16"PRIxREGISTER", tp=%#16"PRIxREGISTER"\n",
tf->tf_ra, tf->tf_sp, tf->tf_gp, tf->tf_tp);
@@ -281,10 +281,10 @@ trap_pagefault_fixup(struct trapframe *t
static bool
trap_pagefault(struct trapframe *tf, register_t epc, register_t status,
- register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
+ register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
{
struct proc * const p = curlwp->l_proc;
- const intptr_t addr = trunc_page(badaddr);
+ const intptr_t addr = trunc_page(tval);
if (__predict_false(usertrap_p
&& (false
@@ -313,7 +313,7 @@ trap_pagefault(struct trapframe *tf, reg
if (error) {
trap_ksi_init(ksi, SIGSEGV,
error == EACCES ? SEGV_ACCERR : SEGV_MAPERR,
- (intptr_t)badaddr, cause);
+ (intptr_t)tval, cause);
return false;
}
uvm_grow(p, addr);
@@ -344,32 +344,32 @@ trap_pagefault(struct trapframe *tf, reg
static bool
trap_instruction(struct trapframe *tf, register_t epc, register_t status,
- register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
+ register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
{
if (usertrap_p) {
trap_ksi_init(ksi, SIGILL, ILL_ILLOPC,
- (intptr_t)badaddr, cause);
+ (intptr_t)tval, cause);
}
return false;
}
static bool
trap_misalignment(struct trapframe *tf, register_t epc, register_t status,
- register_t cause, register_t badaddr, bool usertrap_p, ksiginfo_t *ksi)
+ register_t cause, register_t tval, bool usertrap_p, ksiginfo_t *ksi)
{
if (usertrap_p) {
trap_ksi_init(ksi, SIGBUS, BUS_ADRALN,
- (intptr_t)badaddr, cause);
+ (intptr_t)tval, cause);
}
return false;
}
void
cpu_trap(struct trapframe *tf, register_t epc, register_t status,
- register_t cause, register_t badaddr)
+ register_t cause, register_t tval)
{
const u_int fault_mask = 1U << cause;
- const intptr_t addr = badaddr;
+ const intptr_t addr = tval;
const bool usertrap_p = (status & SR_PS) == 0;
bool ok = true;
ksiginfo_t ksi;
