Module Name:    src
Committed By:   skrll
Date:           Wed Nov  4 20:05:47 UTC 2020

Modified Files:
        src/sys/arch/riscv/include: sysreg.h
        src/sys/arch/riscv/riscv: genassym.cf locore.S riscv_machdep.c

Log Message:
Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@


To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/include/sysreg.h
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/riscv/riscv/genassym.cf
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/riscv/riscv/locore.S
cvs rdiff -u -r1.12 -r1.13 src/sys/arch/riscv/riscv/riscv_machdep.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/riscv/include/sysreg.h
diff -u src/sys/arch/riscv/include/sysreg.h:1.9 src/sys/arch/riscv/include/sysreg.h:1.10
--- src/sys/arch/riscv/include/sysreg.h:1.9	Wed Nov  4 06:56:56 2020
+++ src/sys/arch/riscv/include/sysreg.h	Wed Nov  4 20:05:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: sysreg.h,v 1.9 2020/11/04 06:56:56 skrll Exp $ */
+/* $NetBSD: sysreg.h,v 1.10 2020/11/04 20:05:47 skrll Exp $ */
 
 /*
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -167,12 +167,12 @@ riscvreg_fcsr_write_frm(uint32_t __new)
 #define SIE_IM		(SIE_SEI|SIE_UEIE|SIE_STIE|SIE_UTIE|SIE_SSIE|SIE_USIE)
 
 #ifdef _LP64
-#define	SR_USER		(SR_UIE | SR_U64 | SR_S64 | SR_IM)
-#define	SR_USER32	(SR_USER & ~SR_U64)
-#define	SR_KERNEL	(SR_S | SR_UIE | SR_U64 | SR_S64)
+#define	SR_USER		(SR_UIE)
+#define	SR_USER32	(SR_USER)
+#define	SR_KERNEL	(SR_SIE | SR_UIE)
 #else
-#define	SR_USER		(SR_UIE||SR_IM)
-#define	SR_KERNEL	(SR_S|SR_UIE)
+#define	SR_USER		(SR_UIE)
+#define	SR_KERNEL	(SR_SIE | SR_UIE)
 #endif
 
 static inline uint32_t

Index: src/sys/arch/riscv/riscv/genassym.cf
diff -u src/sys/arch/riscv/riscv/genassym.cf:1.9 src/sys/arch/riscv/riscv/genassym.cf:1.10
--- src/sys/arch/riscv/riscv/genassym.cf:1.9	Wed Nov  4 07:51:08 2020
+++ src/sys/arch/riscv/riscv/genassym.cf	Wed Nov  4 20:05:47 2020
@@ -1,4 +1,4 @@
-#	$NetBSD: genassym.cf,v 1.9 2020/11/04 07:51:08 skrll Exp $
+#	$NetBSD: genassym.cf,v 1.10 2020/11/04 20:05:47 skrll Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -62,6 +62,14 @@ define	SR_SIE		SR_SIE
 
 define	CAUSE_SYSCALL	CAUSE_SYSCALL
 
+ifdef _LP64
+define	SATP_MODE_MASK	SATP_MODE
+define	SATP_MODE_SV39	__SHIFTIN(SATP_MODE_SV39, SATP_MODE)
+define	SATP_MODE_SV48	__SHIFTIN(SATP_MODE_SV48, SATP_MODE)
+else
+define	SATP_MODE_SV32	__SHIFTIN(SATP_MODE_SV32, SATP_MODE)
+endif
+
 define	IPL_HIGH	IPL_HIGH
 define	IPL_DDB		IPL_DDB
 define	IPL_SCHED	IPL_SCHED
@@ -108,7 +116,7 @@ define	TF_T6		offsetof(struct trapframe,
 define	TF_GP		offsetof(struct trapframe, tf_reg[_X_GP])
 define	TF_PC		offsetof(struct trapframe, tf_pc)
 define	TF_CAUSE	offsetof(struct trapframe, tf_cause)
-define	TF_TVA	L	offsetof(struct trapframe, tf_tval)
+define	TF_TVAL		offsetof(struct trapframe, tf_tval)
 define	TF_SR		offsetof(struct trapframe, tf_sr)
 
 define	L_CPU		offsetof(struct lwp, l_cpu)

Index: src/sys/arch/riscv/riscv/locore.S
diff -u src/sys/arch/riscv/riscv/locore.S:1.15 src/sys/arch/riscv/riscv/locore.S:1.16
--- src/sys/arch/riscv/riscv/locore.S:1.15	Wed Nov  4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/locore.S	Wed Nov  4 20:05:47 2020
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.15 2020/11/04 07:09:46 skrll Exp $ */
+/* $NetBSD: locore.S,v 1.16 2020/11/04 20:05:47 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -39,15 +39,6 @@ ENTRY_NP(start)
 	// We get loaded and starting running at or near 0, not where we
 	// should be. We need to construct an initial PDETAB
 
-#ifdef _LP64
-	li	t0, SR_U64|SR_S64
-	li	t1, SR_IM|SR_SIE
-	csrs	sstatus, t0
-#else
-	li	t1, SR_IM|SR_U64|SR_S64|SR_EI
-#endif
-	csrc	sstatus, t1
-
 	li	s11, VM_MAX_KERNEL_ADDRESS
 	li	s10, PAGE_SIZE
 	li	s9, USPACE

Index: src/sys/arch/riscv/riscv/riscv_machdep.c
diff -u src/sys/arch/riscv/riscv/riscv_machdep.c:1.12 src/sys/arch/riscv/riscv/riscv_machdep.c:1.13
--- src/sys/arch/riscv/riscv/riscv_machdep.c:1.12	Wed Nov  4 07:09:46 2020
+++ src/sys/arch/riscv/riscv/riscv_machdep.c	Wed Nov  4 20:05:47 2020
@@ -1,4 +1,4 @@
-/*	$NetBSD: riscv_machdep.c,v 1.12 2020/11/04 07:09:46 skrll Exp $	*/
+/*	$NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 
 #include "opt_modular.h"
 
-__RCSID("$NetBSD: riscv_machdep.c,v 1.12 2020/11/04 07:09:46 skrll Exp $");
+__RCSID("$NetBSD: riscv_machdep.c,v 1.13 2020/11/04 20:05:47 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -124,7 +124,9 @@ md_child_return(struct lwp *l)
 
 	tf->tf_a0 = 0;
 	tf->tf_a1 = 1;
+#ifdef FPE
 	tf->tf_sr &= ~SR_EF;		/* Disable FP as we can't be them. */
+#endif
 }
 
 void

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