Module Name: src
Committed By: matt
Date: Fri Dec 23 17:55:50 UTC 2011
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cpuregs.h
Log Message:
Correct XLP processor ids, add 1074K processor id. Increase ASID space
to 10 bits for MIPS3+ cpus.
To generate a diff of this commit:
cvs rdiff -u -r1.74.28.22 -r1.74.28.23 src/sys/arch/mips/include/cpuregs.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cpuregs.h
diff -u src/sys/arch/mips/include/cpuregs.h:1.74.28.22 src/sys/arch/mips/include/cpuregs.h:1.74.28.23
--- src/sys/arch/mips/include/cpuregs.h:1.74.28.22 Fri Nov 4 04:29:32 2011
+++ src/sys/arch/mips/include/cpuregs.h Fri Dec 23 17:55:50 2011
@@ -693,7 +693,7 @@
#define MIPS1_TLB_PID_SHIFT 6
#define MIPS3_TLB_VPN2 0xffffe000
-#define MIPS3_TLB_ASID 0x000000ff
+#define MIPS3_TLB_ASID 0x000003ff
#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
@@ -732,7 +732,11 @@
#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) != 0 && MIPS1 == 0
#define MIPS_TLB_PID_SHIFT 0
#define MIPS_TLB_PID MIPS3_TLB_PID
+#if (MIPS3 + MIPS4) != 0
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
+#else
+#define MIPS_TLB_NUM_PIDS mips_options.mips_num_tlb_asids
+#endif
#endif
@@ -874,6 +878,7 @@
#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
#define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */
+#define MIPS_1074K 0x9a /* MIPS 1074K ISA 32 Rel 2 */
/*
* Alchemy (company ID 3) use the processor ID field to donote the CPU core
@@ -908,13 +913,8 @@
/*
* CPU processor IDs for company ID == 12 (RMI)
*/
-#define MIPS_XLP832 0x10 /* RMI XLP832 ISA 64 Rel 2 */
-#define MIPS_XLP816 0x14 /* RMI XLP816 ISA 64 Rel 2 */
-#define MIPS_XLP432 0x90 /* RMI XLP432 ISA 64 Rel 2 */
-#define MIPS_XLP416 0x94 /* RMI XLP416 ISA 64 Rel 2 */
-#define MIPS_XLP316 0xd4 /* RMI XLP316 ISA 64 Rel 2 */
-#define MIPS_XLP308 0xd5 /* RMI XLP308 ISA 64 Rel 2 */
-#define MIPS_XLP304 0xd7 /* RMI XLP304 ISA 64 Rel 2 */
+#define MIPS_XLP8XX 0x10 /* RMI XLP8XX/XLP4XX ISA 64 Rel 2 */
+#define MIPS_XLP3XX 0x11 /* RMI XLP3XX ISA 64 Rel 2 */
#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
@@ -957,8 +957,5 @@
#ifdef MIPS64_SB1
#include <mips/sb1regs.h>
#endif
-#if (MIPS64_XLR + MIPS64_XLS + MIPS64_XLP) > 0
-#include <mips/rmi/rmixlreg.h>
-#endif
#endif /* _MIPS_CPUREGS_H_ */
