Module Name: src
Committed By: matt
Date: Sat Dec 24 09:51:51 UTC 2011
Modified Files:
src/sys/arch/mips/include [matt-nb5-mips64]: cache_r4k.h
Log Message:
Change macros with embedded asm into static inline functions.
Pass in line_size to asm and gas expand to the proper offsets.
To generate a diff of this commit:
cvs rdiff -u -r1.11 -r1.11.96.1 src/sys/arch/mips/include/cache_r4k.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/mips/include/cache_r4k.h
diff -u src/sys/arch/mips/include/cache_r4k.h:1.11 src/sys/arch/mips/include/cache_r4k.h:1.11.96.1
--- src/sys/arch/mips/include/cache_r4k.h:1.11 Sat Dec 24 20:07:19 2005
+++ src/sys/arch/mips/include/cache_r4k.h Sat Dec 24 09:51:51 2011
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r4k.h,v 1.11 2005/12/24 20:07:19 perry Exp $ */
+/* $NetBSD: cache_r4k.h,v 1.11.96.1 2011/12/24 09:51:51 matt Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -62,278 +62,235 @@
*
* Perform the specified cache operation on a single line.
*/
-#define cache_op_r4k_line(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0(%0) \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+static inline void
+cache_op_r4k_line(vaddr_t va, u_int op)
+{
+ __asm volatile(
+ ".set push" "\n\t"
+ ".set noreorder" "\n\t"
+ "cache %[op], 0(%[va])" "\n\t"
+ ".set pop"
+ :
+ : [va] "r" (va), [op] "i" (op)
+ : "memory");
+}
+
+/*
+ * cache_r4k_op_8lines_NN:
+ *
+ * Perform the specified cache operation on 8 n-byte cache lines.
+ */
+static inline void
+cache_r4k_op_8lines_NN(size_t n, vaddr_t va, u_int op)
+{
+ __asm volatile(
+ ".set push" "\n\t"
+ ".set noreorder" "\n\t"
+ "cache %[op], (0*%[n])(%[va])" "\n\t"
+ "cache %[op], (1*%[n])(%[va])" "\n\t"
+ "cache %[op], (2*%[n])(%[va])" "\n\t"
+ "cache %[op], (3*%[n])(%[va])" "\n\t"
+ "cache %[op], (4*%[n])(%[va])" "\n\t"
+ "cache %[op], (5*%[n])(%[va])" "\n\t"
+ "cache %[op], (6*%[n])(%[va])" "\n\t"
+ "cache %[op], (7*%[n])(%[va])" "\n\t"
+ ".set pop"
+ :
+ : [va] "r" (va), [op] "i" (op), [n] "n" (n)
+ : "memory");
+}
/*
* cache_r4k_op_8lines_16:
- *
* Perform the specified cache operation on 8 16-byte cache lines.
- */
-#define cache_r4k_op_8lines_16(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x00(%0); cache %1, 0x10(%0) \n\t" \
- "cache %1, 0x20(%0); cache %1, 0x30(%0) \n\t" \
- "cache %1, 0x40(%0); cache %1, 0x50(%0) \n\t" \
- "cache %1, 0x60(%0); cache %1, 0x70(%0) \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-/*
* cache_r4k_op_8lines_32:
- *
* Perform the specified cache operation on 8 32-byte cache lines.
*/
-#define cache_r4k_op_8lines_32(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x00(%0); cache %1, 0x20(%0) \n\t" \
- "cache %1, 0x40(%0); cache %1, 0x60(%0) \n\t" \
- "cache %1, 0x80(%0); cache %1, 0xa0(%0) \n\t" \
- "cache %1, 0xc0(%0); cache %1, 0xe0(%0) \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+#define cache_r4k_op_8lines_16(va, op) \
+ cache_r4k_op_8lines_NN(16, (va), (op))
+#define cache_r4k_op_8lines_32(va, op) \
+ cache_r4k_op_8lines_NN(32, (va), (op))
+
+/*
+ * cache_r4k_op_32lines_NN:
+ *
+ * Perform the specified cache operation on 32 n-byte cache lines.
+ */
+static inline void
+cache_r4k_op_32lines_NN(size_t n, vaddr_t va, u_int op)
+{
+ __asm volatile(
+ ".set push" "\n\t"
+ ".set noreorder" "\n\t"
+ "cache %[op], (0*%[n])(%[va])" "\n\t"
+ "cache %[op], (1*%[n])(%[va])" "\n\t"
+ "cache %[op], (2*%[n])(%[va])" "\n\t"
+ "cache %[op], (3*%[n])(%[va])" "\n\t"
+ "cache %[op], (4*%[n])(%[va])" "\n\t"
+ "cache %[op], (5*%[n])(%[va])" "\n\t"
+ "cache %[op], (6*%[n])(%[va])" "\n\t"
+ "cache %[op], (7*%[n])(%[va])" "\n\t"
+ "cache %[op], (8*%[n])(%[va])" "\n\t"
+ "cache %[op], (9*%[n])(%[va])" "\n\t"
+ "cache %[op], (10*%[n])(%[va])" "\n\t"
+ "cache %[op], (11*%[n])(%[va])" "\n\t"
+ "cache %[op], (12*%[n])(%[va])" "\n\t"
+ "cache %[op], (13*%[n])(%[va])" "\n\t"
+ "cache %[op], (14*%[n])(%[va])" "\n\t"
+ "cache %[op], (15*%[n])(%[va])" "\n\t"
+ "cache %[op], (16*%[n])(%[va])" "\n\t"
+ "cache %[op], (17*%[n])(%[va])" "\n\t"
+ "cache %[op], (18*%[n])(%[va])" "\n\t"
+ "cache %[op], (19*%[n])(%[va])" "\n\t"
+ "cache %[op], (20*%[n])(%[va])" "\n\t"
+ "cache %[op], (21*%[n])(%[va])" "\n\t"
+ "cache %[op], (22*%[n])(%[va])" "\n\t"
+ "cache %[op], (23*%[n])(%[va])" "\n\t"
+ "cache %[op], (24*%[n])(%[va])" "\n\t"
+ "cache %[op], (25*%[n])(%[va])" "\n\t"
+ "cache %[op], (26*%[n])(%[va])" "\n\t"
+ "cache %[op], (27*%[n])(%[va])" "\n\t"
+ "cache %[op], (28*%[n])(%[va])" "\n\t"
+ "cache %[op], (29*%[n])(%[va])" "\n\t"
+ "cache %[op], (30*%[n])(%[va])" "\n\t"
+ "cache %[op], (31*%[n])(%[va])" "\n\t"
+ ".set pop"
+ :
+ : [va] "r" (va), [op] "i" (op), [n] "n" (n)
+ : "memory");
+}
/*
* cache_r4k_op_32lines_16:
*
- * Perform the specified cache operation on 32 16-byte
- * cache lines.
- */
-#define cache_r4k_op_32lines_16(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x000(%0); cache %1, 0x010(%0); \n\t" \
- "cache %1, 0x020(%0); cache %1, 0x030(%0); \n\t" \
- "cache %1, 0x040(%0); cache %1, 0x050(%0); \n\t" \
- "cache %1, 0x060(%0); cache %1, 0x070(%0); \n\t" \
- "cache %1, 0x080(%0); cache %1, 0x090(%0); \n\t" \
- "cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \n\t" \
- "cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \n\t" \
- "cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \n\t" \
- "cache %1, 0x100(%0); cache %1, 0x110(%0); \n\t" \
- "cache %1, 0x120(%0); cache %1, 0x130(%0); \n\t" \
- "cache %1, 0x140(%0); cache %1, 0x150(%0); \n\t" \
- "cache %1, 0x160(%0); cache %1, 0x170(%0); \n\t" \
- "cache %1, 0x180(%0); cache %1, 0x190(%0); \n\t" \
- "cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \n\t" \
- "cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \n\t" \
- "cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-/*
- * cache_r4k_op_32lines_32:
- *
- * Perform the specified cache operation on 32 32-byte
- * cache lines.
+ * Perform the specified cache operation on 32 16-byte cache lines.
*/
-#define cache_r4k_op_32lines_32(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x000(%0); cache %1, 0x020(%0); \n\t" \
- "cache %1, 0x040(%0); cache %1, 0x060(%0); \n\t" \
- "cache %1, 0x080(%0); cache %1, 0x0a0(%0); \n\t" \
- "cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \n\t" \
- "cache %1, 0x100(%0); cache %1, 0x120(%0); \n\t" \
- "cache %1, 0x140(%0); cache %1, 0x160(%0); \n\t" \
- "cache %1, 0x180(%0); cache %1, 0x1a0(%0); \n\t" \
- "cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \n\t" \
- "cache %1, 0x200(%0); cache %1, 0x220(%0); \n\t" \
- "cache %1, 0x240(%0); cache %1, 0x260(%0); \n\t" \
- "cache %1, 0x280(%0); cache %1, 0x2a0(%0); \n\t" \
- "cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \n\t" \
- "cache %1, 0x300(%0); cache %1, 0x320(%0); \n\t" \
- "cache %1, 0x340(%0); cache %1, 0x360(%0); \n\t" \
- "cache %1, 0x380(%0); cache %1, 0x3a0(%0); \n\t" \
- "cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-/*
- * cache_r4k_op_32lines_128:
- *
- * Perform the specified cache operation on 32 128-byte
- * cache lines.
- */
-#define cache_r4k_op_32lines_128(va, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x0000(%0); cache %1, 0x0080(%0); \n\t" \
- "cache %1, 0x0100(%0); cache %1, 0x0180(%0); \n\t" \
- "cache %1, 0x0200(%0); cache %1, 0x0280(%0); \n\t" \
- "cache %1, 0x0300(%0); cache %1, 0x0380(%0); \n\t" \
- "cache %1, 0x0400(%0); cache %1, 0x0480(%0); \n\t" \
- "cache %1, 0x0500(%0); cache %1, 0x0580(%0); \n\t" \
- "cache %1, 0x0600(%0); cache %1, 0x0680(%0); \n\t" \
- "cache %1, 0x0700(%0); cache %1, 0x0780(%0); \n\t" \
- "cache %1, 0x0800(%0); cache %1, 0x0880(%0); \n\t" \
- "cache %1, 0x0900(%0); cache %1, 0x0980(%0); \n\t" \
- "cache %1, 0x0a00(%0); cache %1, 0x0a80(%0); \n\t" \
- "cache %1, 0x0b00(%0); cache %1, 0x0b80(%0); \n\t" \
- "cache %1, 0x0c00(%0); cache %1, 0x0c80(%0); \n\t" \
- "cache %1, 0x0d00(%0); cache %1, 0x0d80(%0); \n\t" \
- "cache %1, 0x0e00(%0); cache %1, 0x0e80(%0); \n\t" \
- "cache %1, 0x0f00(%0); cache %1, 0x0f80(%0); \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+#define cache_r4k_op_32lines_16(va, op) \
+ cache_r4k_op_32lines_NN(16, (va), (op))
+#define cache_r4k_op_32lines_32(va, op) \
+ cache_r4k_op_32lines_NN(32, (va), (op))
+#define cache_r4k_op_32lines_128(va, op) \
+ cache_r4k_op_32lines_NN(128, (va), (op))
/*
* cache_r4k_op_16lines_16_2way:
- *
- * Perform the specified cache operation on 16 16-byte
- * cache lines, 2-ways.
+ * Perform the specified cache operation on 16 n-byte cache lines, 2-ways.
*/
-#define cache_r4k_op_16lines_16_2way(va1, va2, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
- "cache %2, 0x010(%0); cache %2, 0x010(%1); \n\t" \
- "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \
- "cache %2, 0x030(%0); cache %2, 0x030(%1); \n\t" \
- "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
- "cache %2, 0x050(%0); cache %2, 0x050(%1); \n\t" \
- "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \
- "cache %2, 0x070(%0); cache %2, 0x070(%1); \n\t" \
- "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
- "cache %2, 0x090(%0); cache %2, 0x090(%1); \n\t" \
- "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \
- "cache %2, 0x0b0(%0); cache %2, 0x0b0(%1); \n\t" \
- "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
- "cache %2, 0x0d0(%0); cache %2, 0x0d0(%1); \n\t" \
- "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \
- "cache %2, 0x0f0(%0); cache %2, 0x0f0(%1); \n\t" \
- ".set reorder" \
- : \
- : "r" (va1), "r" (va2), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+static inline void
+cache_r4k_op_16lines_NN_2way(size_t n, vaddr_t va1, vaddr_t va2, u_int op)
+{
+ __asm volatile(
+ ".set push" "\n\t"
+ ".set noreorder" "\n\t"
+ "cache %[op], (0*%[n])(%[va1])" "\n\t"
+ "cache %[op], (0*%[n])(%[va2])" "\n\t"
+ "cache %[op], (1*%[n])(%[va1])" "\n\t"
+ "cache %[op], (1*%[n])(%[va2])" "\n\t"
+ "cache %[op], (2*%[n])(%[va1])" "\n\t"
+ "cache %[op], (2*%[n])(%[va2])" "\n\t"
+ "cache %[op], (3*%[n])(%[va1])" "\n\t"
+ "cache %[op], (3*%[n])(%[va2])" "\n\t"
+ "cache %[op], (4*%[n])(%[va1])" "\n\t"
+ "cache %[op], (4*%[n])(%[va2])" "\n\t"
+ "cache %[op], (5*%[n])(%[va1])" "\n\t"
+ "cache %[op], (5*%[n])(%[va2])" "\n\t"
+ "cache %[op], (6*%[n])(%[va1])" "\n\t"
+ "cache %[op], (6*%[n])(%[va2])" "\n\t"
+ "cache %[op], (7*%[n])(%[va1])" "\n\t"
+ "cache %[op], (7*%[n])(%[va2])" "\n\t"
+ "cache %[op], (8*%[n])(%[va1])" "\n\t"
+ "cache %[op], (8*%[n])(%[va2])" "\n\t"
+ "cache %[op], (9*%[n])(%[va1])" "\n\t"
+ "cache %[op], (9*%[n])(%[va2])" "\n\t"
+ "cache %[op], (10*%[n])(%[va1])" "\n\t"
+ "cache %[op], (10*%[n])(%[va2])" "\n\t"
+ "cache %[op], (11*%[n])(%[va1])" "\n\t"
+ "cache %[op], (11*%[n])(%[va2])" "\n\t"
+ "cache %[op], (12*%[n])(%[va1])" "\n\t"
+ "cache %[op], (12*%[n])(%[va2])" "\n\t"
+ "cache %[op], (13*%[n])(%[va1])" "\n\t"
+ "cache %[op], (13*%[n])(%[va2])" "\n\t"
+ "cache %[op], (14*%[n])(%[va1])" "\n\t"
+ "cache %[op], (14*%[n])(%[va2])" "\n\t"
+ "cache %[op], (15*%[n])(%[va1])" "\n\t"
+ "cache %[op], (15*%[n])(%[va2])" "\n\t"
+ ".set pop"
+ :
+ : [va1] "r" (va1), [va2] "r" (va2), [op] "i" (op), [n] "n" (n)
+ : "memory");
+}
/*
+ * cache_r4k_op_16lines_16_2way:
+ * Perform the specified cache operation on 16 16-byte cache lines, 2-ways.
* cache_r4k_op_16lines_32_2way:
- *
- * Perform the specified cache operation on 16 32-byte
- * cache lines, 2-ways.
+ * Perform the specified cache operation on 16 32-byte cache lines, 2-ways.
*/
+#define cache_r4k_op_16lines_16_2way(va1, va2, op) \
+ cache_r4k_op_16lines_NN_2way(16, (va1), (va2), (op)
#define cache_r4k_op_16lines_32_2way(va1, va2, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
- "cache %2, 0x020(%0); cache %2, 0x020(%1); \n\t" \
- "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
- "cache %2, 0x060(%0); cache %2, 0x060(%1); \n\t" \
- "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
- "cache %2, 0x0a0(%0); cache %2, 0x0a0(%1); \n\t" \
- "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
- "cache %2, 0x0e0(%0); cache %2, 0x0e0(%1); \n\t" \
- "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \
- "cache %2, 0x120(%0); cache %2, 0x120(%1); \n\t" \
- "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \
- "cache %2, 0x160(%0); cache %2, 0x160(%1); \n\t" \
- "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \
- "cache %2, 0x1a0(%0); cache %2, 0x1a0(%1); \n\t" \
- "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \
- "cache %2, 0x1e0(%0); cache %2, 0x1e0(%1); \n\t" \
- ".set reorder" \
- : \
- : "r" (va1), "r" (va2), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+ cache_r4k_op_16lines_NN_2way(32, (va1), (va2), (op)
/*
- * cache_r4k_op_8lines_16_4way:
- *
- * Perform the specified cache operation on 8 16-byte
- * cache lines, 4-ways.
+ * cache_r4k_op_8lines_NN_4way:
+ * Perform the specified cache operation on 8 n-byte cache lines, 4-ways.
*/
-#define cache_r4k_op_8lines_16_4way(va1, va2, va3, va4, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \
- "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \
- "cache %4, 0x010(%0); cache %4, 0x010(%1); \n\t" \
- "cache %4, 0x010(%2); cache %4, 0x010(%3); \n\t" \
- "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \
- "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \
- "cache %4, 0x030(%0); cache %4, 0x030(%1); \n\t" \
- "cache %4, 0x030(%2); cache %4, 0x030(%3); \n\t" \
- "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \
- "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \
- "cache %4, 0x050(%0); cache %4, 0x050(%1); \n\t" \
- "cache %4, 0x050(%2); cache %4, 0x050(%3); \n\t" \
- "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \
- "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \
- "cache %4, 0x070(%0); cache %4, 0x070(%1); \n\t" \
- "cache %4, 0x070(%2); cache %4, 0x070(%3); \n\t" \
- ".set reorder" \
- : \
- : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
+static inline void
+cache_r4k_op_8lines_NN_4way(size_t n, vaddr_t va1, vaddr_t va2, vaddr_t va3,
+ vaddr_t va4, u_int op)
+{
+ __asm volatile(
+ ".set push" "\n\t"
+ ".set noreorder" "\n\t"
+ "cache %[op], (0*%[n])(%[va1])" "\n\t"
+ "cache %[op], (0*%[n])(%[va2])" "\n\t"
+ "cache %[op], (0*%[n])(%[va3])" "\n\t"
+ "cache %[op], (0*%[n])(%[va4])" "\n\t"
+ "cache %[op], (1*%[n])(%[va1])" "\n\t"
+ "cache %[op], (1*%[n])(%[va2])" "\n\t"
+ "cache %[op], (1*%[n])(%[va3])" "\n\t"
+ "cache %[op], (1*%[n])(%[va4])" "\n\t"
+ "cache %[op], (2*%[n])(%[va1])" "\n\t"
+ "cache %[op], (2*%[n])(%[va2])" "\n\t"
+ "cache %[op], (2*%[n])(%[va3])" "\n\t"
+ "cache %[op], (2*%[n])(%[va4])" "\n\t"
+ "cache %[op], (3*%[n])(%[va1])" "\n\t"
+ "cache %[op], (3*%[n])(%[va2])" "\n\t"
+ "cache %[op], (3*%[n])(%[va3])" "\n\t"
+ "cache %[op], (3*%[n])(%[va4])" "\n\t"
+ "cache %[op], (4*%[n])(%[va1])" "\n\t"
+ "cache %[op], (4*%[n])(%[va2])" "\n\t"
+ "cache %[op], (4*%[n])(%[va3])" "\n\t"
+ "cache %[op], (4*%[n])(%[va4])" "\n\t"
+ "cache %[op], (5*%[n])(%[va1])" "\n\t"
+ "cache %[op], (5*%[n])(%[va2])" "\n\t"
+ "cache %[op], (5*%[n])(%[va3])" "\n\t"
+ "cache %[op], (5*%[n])(%[va4])" "\n\t"
+ "cache %[op], (6*%[n])(%[va1])" "\n\t"
+ "cache %[op], (6*%[n])(%[va2])" "\n\t"
+ "cache %[op], (6*%[n])(%[va3])" "\n\t"
+ "cache %[op], (6*%[n])(%[va4])" "\n\t"
+ "cache %[op], (7*%[n])(%[va1])" "\n\t"
+ "cache %[op], (7*%[n])(%[va2])" "\n\t"
+ "cache %[op], (7*%[n])(%[va3])" "\n\t"
+ "cache %[op], (7*%[n])(%[va4])" "\n\t"
+ ".set pop"
+ :
+ : [va1] "r" (va1), [va2] "r" (va2),
+ [va3] "r" (va3), [va4] "r" (va4),
+ [op] "i" (op), [n] "n" (n)
+ : "memory");
+}
/*
+ * cache_r4k_op_8lines_16_4way:
+ * Perform the specified cache operation on 8 16-byte cache lines, 4-ways.
* cache_r4k_op_8lines_32_4way:
- *
- * Perform the specified cache operation on 8 32-byte
- * cache lines, 4-ways.
+ * Perform the specified cache operation on 8 32-byte cache lines, 4-ways.
*/
-#define cache_r4k_op_8lines_32_4way(va1, va2, va3, va4, op) \
-do { \
- __asm volatile( \
- ".set noreorder \n\t" \
- "cache %4, 0x000(%0); cache %4, 0x000(%1); \n\t" \
- "cache %4, 0x000(%2); cache %4, 0x000(%3); \n\t" \
- "cache %4, 0x020(%0); cache %4, 0x020(%1); \n\t" \
- "cache %4, 0x020(%2); cache %4, 0x020(%3); \n\t" \
- "cache %4, 0x040(%0); cache %4, 0x040(%1); \n\t" \
- "cache %4, 0x040(%2); cache %4, 0x040(%3); \n\t" \
- "cache %4, 0x060(%0); cache %4, 0x060(%1); \n\t" \
- "cache %4, 0x060(%2); cache %4, 0x060(%3); \n\t" \
- "cache %4, 0x080(%0); cache %4, 0x080(%1); \n\t" \
- "cache %4, 0x080(%2); cache %4, 0x080(%3); \n\t" \
- "cache %4, 0x0a0(%0); cache %4, 0x0a0(%1); \n\t" \
- "cache %4, 0x0a0(%2); cache %4, 0x0a0(%3); \n\t" \
- "cache %4, 0x0c0(%0); cache %4, 0x0c0(%1); \n\t" \
- "cache %4, 0x0c0(%2); cache %4, 0x0c0(%3); \n\t" \
- "cache %4, 0x0e0(%0); cache %4, 0x0e0(%1); \n\t" \
- "cache %4, 0x0e0(%2); cache %4, 0x0e0(%3); \n\t" \
- ".set reorder" \
- : \
- : "r" (va1), "r" (va2), "r" (va3), "r" (va4), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
+#define cache_r4k_op_8lines_16_4way(va1, va2, va3, va4, op) \
+ cache_r4k_op_8lines_NN_4way(16, (va1), (va2), (va3), (va4), (op))
+#define cache_r4k_op_8lines_32_4way(va1, va2, va3, va4, op) \
+ cache_r4k_op_8lines_NN_4way(32, (va1), (va2), (va3), (va4), (op))
void r4k_icache_sync_all_16(void);
void r4k_icache_sync_range_16(vaddr_t, vsize_t);
