Module Name: src
Committed By: jmcneill
Date: Fri Oct 17 20:18:41 UTC 2014
Modified Files:
src/sys/arch/arm/allwinner: awin_gige.c
Log Message:
support both MII and RGMII phy types
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/allwinner/awin_gige.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/allwinner/awin_gige.c
diff -u src/sys/arch/arm/allwinner/awin_gige.c:1.8 src/sys/arch/arm/allwinner/awin_gige.c:1.9
--- src/sys/arch/arm/allwinner/awin_gige.c:1.8 Sat Oct 4 15:25:15 2014
+++ src/sys/arch/arm/allwinner/awin_gige.c Fri Oct 17 20:18:41 2014
@@ -31,7 +31,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.8 2014/10/04 15:25:15 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: awin_gige.c,v 1.9 2014/10/17 20:18:41 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -92,6 +92,9 @@ awin_gige_attach(device_t parent, device
struct awin_gige_softc * const sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
+ prop_dictionary_t cfg = device_properties(self);
+ uint32_t clkreg;
+ const char *phy_type;
sc->sc_core.sc_dev = self;
@@ -123,13 +126,21 @@ awin_gige_attach(device_t parent, device
*/
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING1_REG, AWIN_AHB_GATING1_GMAC, 0);
+
/*
- * We use RGMII phy mode, set up clock accordingly
+ * PHY clock setup
*/
- bus_space_write_4(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_GMAC_CLK_REG, 4); /* GPIT = RMII */
+ if (!prop_dictionary_get_cstring_nocopy(cfg, "phy-type", &phy_type))
+ phy_type = "rgmii";
+ if (strcmp(phy_type, "rgmii")) {
+ clkreg = AWIN_GMAC_CLK_PIT | AWIN_GMAC_CLK_TCS_INT_RGMII;
+ } else if (strcmp(phy_type, "mii")) {
+ clkreg = AWIN_GMAC_CLK_TCS_MII;
+ } else {
+ panic("unknown phy type '%s'", phy_type);
+ }
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
- AWIN_GMAC_CLK_REG, 2, 0); /* GTCS = internal transmit clock */
+ AWIN_GMAC_CLK_REG, clkreg, AWIN_GMAC_CLK_PIT|AWIN_GMAC_CLK_TCS);
dwc_gmac_attach(&sc->sc_core, 2);
}
