Module Name:    src
Committed By:   skrll
Date:           Fri May 15 10:57:55 UTC 2015

Modified Files:
        src/sys/arch/arm/cortex: a9_mpsubr.S

Log Message:
Make sure TLB is invalidated and ACTLR.SMP is set on ARM A15.  ACTLR.SMP
enables the processor to receive instruction cache, BTB and TLB main-
tenance operations from other processors


To generate a diff of this commit:
cvs rdiff -u -r1.36 -r1.37 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.36 src/sys/arch/arm/cortex/a9_mpsubr.S:1.37
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.36	Sun May  3 16:18:51 2015
+++ src/sys/arch/arm/cortex/a9_mpsubr.S	Fri May 15 10:57:55 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9_mpsubr.S,v 1.36 2015/05/03 16:18:51 matt Exp $	*/
+/*	$NetBSD: a9_mpsubr.S,v 1.37 2015/05/15 10:57:55 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -450,7 +450,7 @@ cortex_init:
 	XPUTC(#'2')
 #endif /* CORTEXA5 || CORTEXA9 */
 
-#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA17)
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
 	//
 	// The MMU is off.  Make sure the TLB is invalidated before
 	// turning on SMP.
@@ -461,8 +461,8 @@ cortex_init:
 
 	// For the A7, SMP must be on ldrex/strex to work.
 	//
-#if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA17)
-#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA17)
+#if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
+#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
 	//
 	// Step 4a, set ACTLR.SMP=1
 	//
@@ -485,7 +485,7 @@ cortex_init:
 	mcr	p15, 0, r0, c1, c0, 1		// ACTLR write
 	isb
 	dsb
-#endif	/* A5 || A7 || A9 || A17 */
+#endif	/* A5 || A7 || A9 || A15 || A17 */
 #endif	/* MULTIPROCESSOR */
 
 	//

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