Module Name: src
Committed By: matt
Date: Thu May 28 02:23:18 UTC 2015
Modified Files:
src/sys/arch/arm/cortex: a9_mpsubr.S
Log Message:
A15 change for > 2 cores.
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/arm/cortex/a9_mpsubr.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.38 src/sys/arch/arm/cortex/a9_mpsubr.S:1.39
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.38 Sun May 17 06:12:40 2015
+++ src/sys/arch/arm/cortex/a9_mpsubr.S Thu May 28 02:23:18 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: a9_mpsubr.S,v 1.38 2015/05/17 06:12:40 matt Exp $ */
+/* $NetBSD: a9_mpsubr.S,v 1.39 2015/05/28 02:23:18 matt Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -469,6 +469,14 @@ cortex_init:
mrc p15, 0, r0, c1, c0, 1 // ACTLR read
orr r0, r0, #CORTEXA9_AUXCTL_SMP // enable SMP
+#if defined(CPU_CORTEXA15)
+ // The A15 requires snoop-delayed exclusive handling to be set
+ // if there are 3 or more CPUs.
+ mrc p15, 1, r2, c9, c0, 2 // L2CTRL read
+ ubfx r2, r2, #25, #1 // bit 25 is set when 3+ CPUs
+ bfi r0, r2, #31, #1 // copy it to bit 31 in ACTRL
+#endif
+
#if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA9)
//
// Step 4a (continued on A5/A9), ACTLR.FW=1)
