Module Name: src
Committed By: jakllsch
Date: Sat Nov 21 16:48:33 UTC 2015
Modified Files:
src/sys/arch/arm/nvidia: tegra_mcreg.h
Log Message:
Add a bunch of hopefully-useful Tegra MC register bits.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/nvidia/tegra_mcreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/tegra_mcreg.h
diff -u src/sys/arch/arm/nvidia/tegra_mcreg.h:1.1 src/sys/arch/arm/nvidia/tegra_mcreg.h:1.2
--- src/sys/arch/arm/nvidia/tegra_mcreg.h:1.1 Sun Mar 29 10:41:59 2015
+++ src/sys/arch/arm/nvidia/tegra_mcreg.h Sat Nov 21 16:48:33 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_mcreg.h,v 1.1 2015/03/29 10:41:59 jmcneill Exp $ */
+/* $NetBSD: tegra_mcreg.h,v 1.2 2015/11/21 16:48:33 jakllsch Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,6 +29,50 @@
#ifndef _ARM_TEGRA_MCREG_H
#define _ARM_TEGRA_MCREG_H
+#define MC_INTSTATUS_REG 0x00
+#define MC_INTMASK_REG 0x04
+
+#define MC_INT_DECERR_MTS __BIT(16)
+#define MC_INT_SECERR_SEC __BIT(13)
+#define MC_INT_DECERR_VPR __BIT(12)
+#define MC_INT_INVALID_APB_ASID_UPDATE __BIT(11)
+#define MC_INT_INVALID_SMMU_PAGE __BIT(10)
+#define MC_INT_SECURITY_VIOLATION __BIT(8)
+#define MC_INT_ARBITRATION_EMEM __BIT(9)
+#define MC_INT_DECERR_EMEM __BIT(6)
+#define MC_INT__ALL (MC_INT_DECERR_MTS | \
+ MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | \
+ MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE | \
+ MC_INT_SECURITY_VIOLATION | MC_INT_ARBITRATION_EMEM | \
+ MC_INT_DECERR_EMEM)
+
+#define MC_ERR_STATUS_REG 0x08
+
+#define MC_ERR_TYPE __BITS(30,28)
+#define MC_ERR_INVALID_SMMU_PAGE_READABLE __BIT(27)
+#define MC_ERR_INVALID_SMMU_PAGE_WRITABLE __BIT(26)
+#define MC_ERR_INVALID_SMMU_PAGE_NONSECURE __BIT(25)
+#define MC_ERR_ADDR_HI __BITS(21,20)
+#define MC_ERR_SWAP __BIT(18)
+#define MC_ERR_SECURITY __BIT(17)
+#define MC_ERR_RW __BIT(16)
+#define MC_ERR_RW_READ 0
+#define MC_ERR_RW_WRITE 1
+#define MC_ERR_ADR1 __BITS(14,12)
+#define MC_ERR_ID __BITS(6,0)
+
+#define MC_ERR_ADR_REG 0x0c
+
+#define MC_SMMU_CONFIG_REG 0x10
+#define MC_SMMU_ENABLE __BIT(0)
+
+#define MC_SMMU_TLB_CONFIG_REG 0x14
+#define MC_SMMU_PTC_CONFIG_REG 0x18
+#define MC_SMMU_PTB_ASID_REG 0x1c
+#define MC_SMMU_PTB_DATA_REG 0x20
+#define MC_SMMU_TLB_FLUSH_REG 0x30
+#define MC_SMMU_PTC_FLUSH_REG 0x34
+
#define MC_EMEM_CFG_0_REG 0x50
#define MC_EMEM_CFG_0_EMEM_BOM __BIT(31)
