Module Name: src
Committed By: jmcneill
Date: Sat Nov 21 22:55:32 UTC 2015
Modified Files:
src/sys/arch/arm/nvidia: files.tegra tegra_car.c tegra_carreg.h
tegra_intr.h tegra_io.c tegra_reg.h tegra_var.h
Added Files:
src/sys/arch/arm/nvidia: tegra_soctherm.c tegra_socthermreg.h
Log Message:
Add SOC_THERM temperature sensor driver:
# envstat -d tegrasoctherm0
Current CritMax WarnMax WarnMin CritMin Unit
CPU0: 27.500 degC
CPU1: 27.500 degC
CPU2: 29.500 degC
CPU3: 29.000 degC
MEM0: 26.500 degC
MEM1: 27.000 degC
GPU: 27.000 degC
PLLX: 28.000 degC
To generate a diff of this commit:
cvs rdiff -u -r1.23 -r1.24 src/sys/arch/arm/nvidia/files.tegra
cvs rdiff -u -r1.29 -r1.30 src/sys/arch/arm/nvidia/tegra_car.c
cvs rdiff -u -r1.21 -r1.22 src/sys/arch/arm/nvidia/tegra_carreg.h
cvs rdiff -u -r1.10 -r1.11 src/sys/arch/arm/nvidia/tegra_intr.h
cvs rdiff -u -r1.20 -r1.21 src/sys/arch/arm/nvidia/tegra_io.c
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/nvidia/tegra_reg.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/nvidia/tegra_soctherm.c \
src/sys/arch/arm/nvidia/tegra_socthermreg.h
cvs rdiff -u -r1.27 -r1.28 src/sys/arch/arm/nvidia/tegra_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/nvidia/files.tegra
diff -u src/sys/arch/arm/nvidia/files.tegra:1.23 src/sys/arch/arm/nvidia/files.tegra:1.24
--- src/sys/arch/arm/nvidia/files.tegra:1.23 Sat Nov 21 12:09:39 2015
+++ src/sys/arch/arm/nvidia/files.tegra Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-# $NetBSD: files.tegra,v 1.23 2015/11/21 12:09:39 jmcneill Exp $
+# $NetBSD: files.tegra,v 1.24 2015/11/21 22:55:32 jmcneill Exp $
#
# Configuration info for NVIDIA Tegra ARM Peripherals
#
@@ -91,6 +91,11 @@ file arch/arm/nvidia/tegra_ehci.c tegra
attach sdhc at tegraio with tegra_sdhc
file arch/arm/nvidia/tegra_sdhc.c tegra_sdhc
+# Thermal throttling controller
+device tegrasoctherm: sysmon_envsys
+attach tegrasoctherm at tegraio with tegra_soctherm
+file arch/arm/nvidia/tegra_soctherm.c tegra_soctherm
+
# PCIE
device tegrapcie: pcibus
attach tegrapcie at tegraio with tegra_pcie
Index: src/sys/arch/arm/nvidia/tegra_car.c
diff -u src/sys/arch/arm/nvidia/tegra_car.c:1.29 src/sys/arch/arm/nvidia/tegra_car.c:1.30
--- src/sys/arch/arm/nvidia/tegra_car.c:1.29 Sat Nov 21 12:09:39 2015
+++ src/sys/arch/arm/nvidia/tegra_car.c Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_car.c,v 1.29 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_car.c,v 1.30 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.29 2015/11/21 12:09:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_car.c,v 1.30 2015/11/21 22:55:32 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -882,3 +882,36 @@ tegra_car_fuse_disable(void)
tegra_reg_set_clear(bst, bsh, CAR_CLK_ENB_H_SET_REG, 0, CAR_DEV_H_FUSE);
}
+
+void
+tegra_car_soctherm_enable(void)
+{
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh;
+
+ tegra_car_get_bs(&bst, &bsh);
+
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_SET_REG, CAR_DEV_U_SOC_THERM);
+
+ const u_int soctherm_rate = 51000000;
+ const u_int soctherm_div =
+ howmany(tegra_car_pllp0_rate() * 2, soctherm_rate) - 2;
+ bus_space_write_4(bst, bsh, CAR_CLKSRC_SOC_THERM_REG,
+ __SHIFTIN(soctherm_div, CAR_CLKSRC_SOC_THERM_DIV) |
+ __SHIFTIN(CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0,
+ CAR_CLKSRC_SOC_THERM_SRC));
+ delay(20);
+
+ const u_int tsensor_rate = 400000;
+ const u_int tsensor_div =
+ howmany(TEGRA_REF_FREQ * 2, tsensor_rate) - 2;
+ bus_space_write_4(bst, bsh, CAR_CLKSRC_TSENSOR_REG,
+ __SHIFTIN(tsensor_div, CAR_CLKSRC_TSENSOR_DIV) |
+ __SHIFTIN(CAR_CLKSRC_TSENSOR_SRC_CLK_M, CAR_CLKSRC_TSENSOR_SRC));
+ delay(20);
+
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_V_SET_REG, CAR_DEV_V_TSENSOR);
+ bus_space_write_4(bst, bsh, CAR_CLK_ENB_U_SET_REG, CAR_DEV_U_SOC_THERM);
+
+ bus_space_write_4(bst, bsh, CAR_RST_DEV_U_CLR_REG, CAR_DEV_U_SOC_THERM);
+}
Index: src/sys/arch/arm/nvidia/tegra_carreg.h
diff -u src/sys/arch/arm/nvidia/tegra_carreg.h:1.21 src/sys/arch/arm/nvidia/tegra_carreg.h:1.22
--- src/sys/arch/arm/nvidia/tegra_carreg.h:1.21 Sat Oct 17 21:16:09 2015
+++ src/sys/arch/arm/nvidia/tegra_carreg.h Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_carreg.h,v 1.21 2015/10/17 21:16:09 jmcneill Exp $ */
+/* $NetBSD: tegra_carreg.h,v 1.22 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -358,6 +358,7 @@
#define CAR_DEV_V_I2C4 __BIT(7)
#define CAR_DEV_V_I2S4 __BIT(6)
#define CAR_DEV_V_I2S3 __BIT(5)
+#define CAR_DEV_V_TSENSOR __BIT(4)
#define CAR_DEV_V_MSELECT __BIT(3)
#define CAR_DEV_V_CPULP __BIT(1)
#define CAR_DEV_V_CPUG __BIT(0)
@@ -395,6 +396,11 @@
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0
#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8
+#define CAR_CLKSRC_TSENSOR_REG 0x3b8
+#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29)
+#define CAR_CLKSRC_TSENSOR_SRC_CLK_M 4
+#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0)
+
#define CAR_CLKSRC_HDA2CODEC_2X_REG 0x3e4
#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29)
#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0 0
@@ -477,6 +483,11 @@
#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8)
#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0)
+#define CAR_CLKSRC_SOC_THERM_REG 0x644
+#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29)
+#define CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0 2
+#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0)
+
#define CAR_CLKSRC_HDMI_AUDIO_REG 0x668
#define CAR_CLKSRC_HDMI_AUDIO_SRC __BITS(31,29)
#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0 0
Index: src/sys/arch/arm/nvidia/tegra_intr.h
diff -u src/sys/arch/arm/nvidia/tegra_intr.h:1.10 src/sys/arch/arm/nvidia/tegra_intr.h:1.11
--- src/sys/arch/arm/nvidia/tegra_intr.h:1.10 Wed Nov 18 17:01:39 2015
+++ src/sys/arch/arm/nvidia/tegra_intr.h Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_intr.h,v 1.10 2015/11/18 17:01:39 jakllsch Exp $ */
+/* $NetBSD: tegra_intr.h,v 1.11 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -53,6 +53,7 @@
#define TEGRA_INTR_TMR3 TEGRA_INTR(41)
#define TEGRA_INTR_TMR4 TEGRA_INTR(42)
#define TEGRA_INTR_UARTC TEGRA_INTR(46)
+#define TEGRA_INTR_THERMAL TEGRA_INTR(48)
#define TEGRA_INTR_I2C5 TEGRA_INTR(53)
#define TEGRA_INTR_I2C6 TEGRA_INTR(63)
#define TEGRA_INTR_HOST1X_SYNCPT_COP TEGRA_INTR(64)
Index: src/sys/arch/arm/nvidia/tegra_io.c
diff -u src/sys/arch/arm/nvidia/tegra_io.c:1.20 src/sys/arch/arm/nvidia/tegra_io.c:1.21
--- src/sys/arch/arm/nvidia/tegra_io.c:1.20 Sat Nov 21 12:09:39 2015
+++ src/sys/arch/arm/nvidia/tegra_io.c Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_io.c,v 1.20 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_io.c,v 1.21 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -29,7 +29,7 @@
#include "opt_tegra.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.20 2015/11/21 12:09:39 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_io.c,v 1.21 2015/11/21 22:55:32 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -117,6 +117,8 @@ static const struct tegra_locators tegra
TEGRA_HDA_OFFSET, TEGRA_HDA_SIZE, NOPORT, TEGRA_INTR_HDA },
{ "tegracec",
TEGRA_CEC_OFFSET, TEGRA_CEC_SIZE, NOPORT, TEGRA_INTR_CEC },
+ { "tegrasoctherm",
+ TEGRA_SOC_THERM_OFFSET, TEGRA_SOC_THERM_SIZE, NOPORT, TEGRA_INTR_THERMAL },
};
static const struct tegra_locators tegra_ahb_a2_locators[] = {
Index: src/sys/arch/arm/nvidia/tegra_reg.h
diff -u src/sys/arch/arm/nvidia/tegra_reg.h:1.19 src/sys/arch/arm/nvidia/tegra_reg.h:1.20
--- src/sys/arch/arm/nvidia/tegra_reg.h:1.19 Sat Nov 21 12:09:39 2015
+++ src/sys/arch/arm/nvidia/tegra_reg.h Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_reg.h,v 1.19 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_reg.h,v 1.20 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -130,6 +130,8 @@
#define TEGRA_SDMMC4_SIZE 0x200
#define TEGRA_XUSB_DEV_OFFSET 0x000d0000
#define TEGRA_XUSB_DEV_SIZE 0xa000
+#define TEGRA_SOC_THERM_OFFSET 0x000e2000
+#define TEGRA_SOC_THERM_SIZE 0x1000
/* PPSB */
#define TEGRA_TIMER_OFFSET 0x00005000
Index: src/sys/arch/arm/nvidia/tegra_var.h
diff -u src/sys/arch/arm/nvidia/tegra_var.h:1.27 src/sys/arch/arm/nvidia/tegra_var.h:1.28
--- src/sys/arch/arm/nvidia/tegra_var.h:1.27 Sat Nov 21 12:09:39 2015
+++ src/sys/arch/arm/nvidia/tegra_var.h Sat Nov 21 22:55:32 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_var.h,v 1.27 2015/11/21 12:09:39 jmcneill Exp $ */
+/* $NetBSD: tegra_var.h,v 1.28 2015/11/21 22:55:32 jmcneill Exp $ */
/*-
* Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
@@ -113,6 +113,7 @@ void tegra_car_wdt_enable(u_int, bool);
void tegra_car_gpu_enable(void);
void tegra_car_fuse_enable(void);
void tegra_car_fuse_disable(void);
+void tegra_car_soctherm_enable(void);
struct tegra_gpio_pin;
struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
Added files:
Index: src/sys/arch/arm/nvidia/tegra_soctherm.c
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_soctherm.c:1.1
--- /dev/null Sat Nov 21 22:55:32 2015
+++ src/sys/arch/arm/nvidia/tegra_soctherm.c Sat Nov 21 22:55:32 2015
@@ -0,0 +1,329 @@
+/* $NetBSD: tegra_soctherm.c,v 1.1 2015/11/21 22:55:32 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "locators.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.1 2015/11/21 22:55:32 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/kmem.h>
+
+#include <dev/sysmon/sysmonvar.h>
+
+#include <arm/nvidia/tegra_reg.h>
+#include <arm/nvidia/tegra_socthermreg.h>
+#include <arm/nvidia/tegra_var.h>
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13)
+
+#define FUSE_TSENSOR8_CALIB_REG 0x180
+#define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0)
+#define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10)
+
+#define FUSE_SPARE_REALIGNMENT_REG 0x1fc
+#define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0)
+#define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21)
+
+static int tegra_soctherm_match(device_t, cfdata_t, void *);
+static void tegra_soctherm_attach(device_t, device_t, void *);
+
+struct tegra_soctherm_config {
+ uint32_t init_pdiv;
+ uint32_t init_hotspot_off;
+ uint32_t nominal_calib_ft;
+ uint32_t nominal_calib_cp;
+ uint32_t tall;
+ uint32_t tsample;
+ uint32_t tiddq_en;
+ uint32_t ten_count;
+ uint32_t pdiv;
+ uint32_t tsample_ate;
+ uint32_t pdiv_ate;
+};
+
+static const struct tegra_soctherm_config tegra124_soctherm_config = {
+ .init_pdiv = 0x8888,
+ .init_hotspot_off = 0x60600,
+ .nominal_calib_ft = 105,
+ .nominal_calib_cp = 25,
+ .tall = 16300,
+ .tsample = 120,
+ .tiddq_en = 1,
+ .ten_count = 1,
+ .pdiv = 8,
+ .tsample_ate = 480,
+ .pdiv_ate = 8
+};
+
+struct tegra_soctherm_sensor {
+ envsys_data_t s_data;
+ u_int s_base;
+ u_int s_fuse;
+ int s_fuse_corr_alpha;
+ int s_fuse_corr_beta;
+ int16_t s_therm_a;
+ int16_t s_therm_b;
+};
+
+static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = {
+ { .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098,
+ .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 },
+ { .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084,
+ .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 },
+ { .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088,
+ .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 },
+ { .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c,
+ .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 },
+ { .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158,
+ .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 },
+ { .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c,
+ .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 },
+ { .s_data = { .desc = "GPU" }, .s_base = 0x180, .s_fuse = 0x154,
+ .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 },
+ { .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160,
+ .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 },
+};
+
+struct tegra_soctherm_softc {
+ device_t sc_dev;
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+
+ struct sysmon_envsys *sc_sme;
+ struct tegra_soctherm_sensor *sc_sensors;
+ const struct tegra_soctherm_config *sc_config;
+
+ uint32_t sc_base_cp;
+ uint32_t sc_base_ft;
+ int32_t sc_actual_temp_cp;
+ int32_t sc_actual_temp_ft;
+};
+
+static void tegra_soctherm_init_sensors(struct tegra_soctherm_softc *);
+static void tegra_soctherm_init_sensor(struct tegra_soctherm_softc *,
+ struct tegra_soctherm_sensor *);
+static void tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *);
+static int tegra_soctherm_decodeint(uint32_t, uint32_t);
+static int64_t tegra_soctherm_divide(int64_t, int64_t);
+
+CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc),
+ tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL);
+
+#define SOCTHERM_READ(sc, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
+#define SOCTHERM_WRITE(sc, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
+#define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \
+ tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
+
+#define SENSOR_READ(sc, s, reg) \
+ bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg))
+#define SENSOR_WRITE(sc, s, reg, val) \
+ bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val))
+#define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \
+ tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr))
+
+static int
+tegra_soctherm_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+tegra_soctherm_attach(device_t parent, device_t self, void *aux)
+{
+ struct tegra_soctherm_softc * const sc = device_private(self);
+ struct tegraio_attach_args * const tio = aux;
+ const struct tegra_locators * const loc = &tio->tio_loc;
+
+ sc->sc_dev = self;
+ sc->sc_bst = tio->tio_bst;
+ bus_space_subregion(tio->tio_bst, tio->tio_bsh,
+ loc->loc_offset, loc->loc_size, &sc->sc_bsh);
+
+ aprint_naive("\n");
+ aprint_normal(": SOC_THERM\n");
+
+ if (tegra_chip_id() == CHIP_ID_TEGRA124) {
+ sc->sc_config = &tegra124_soctherm_config;
+ }
+
+ if (sc->sc_config == NULL) {
+ aprint_error_dev(self, "unsupported chip ID\n");
+ return;
+ }
+
+ tegra_car_soctherm_enable();
+
+ tegra_soctherm_init_sensors(sc);
+}
+
+static void
+tegra_soctherm_init_sensors(struct tegra_soctherm_softc *sc)
+{
+ const struct tegra_soctherm_config *config = sc->sc_config;
+ const u_int nsensors = __arraycount(tegra_soctherm_sensors);
+ const size_t len = sizeof(*sc->sc_sensors) * nsensors;
+ uint32_t val;
+ u_int n;
+
+ val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG);
+ sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE);
+ sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE);
+ val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG);
+ const int calib_cp = tegra_soctherm_decodeint(val,
+ FUSE_SPARE_REALIGNMENT_CP);
+ const int calib_ft = tegra_soctherm_decodeint(val,
+ FUSE_SPARE_REALIGNMENT_FT);
+ sc->sc_actual_temp_cp = 2 * config->nominal_calib_cp + calib_cp;
+ sc->sc_actual_temp_ft = 2 * config->nominal_calib_ft + calib_ft;
+
+ sc->sc_sme = sysmon_envsys_create();
+ sc->sc_sme->sme_name = device_xname(sc->sc_dev);
+ sc->sc_sme->sme_cookie = sc;
+ sc->sc_sme->sme_refresh = tegra_soctherm_refresh;
+
+ sc->sc_sensors = kmem_zalloc(len, KM_SLEEP);
+ for (n = 0; n < nsensors; n++) {
+ sc->sc_sensors[n] = tegra_soctherm_sensors[n];
+ tegra_soctherm_init_sensor(sc, &sc->sc_sensors[n]);
+ }
+
+ SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_PDIV_REG, config->init_pdiv);
+ SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_HOTSPOT_OFF_REG,
+ config->init_hotspot_off);
+
+ sysmon_envsys_register(sc->sc_sme);
+}
+
+static void
+tegra_soctherm_init_sensor(struct tegra_soctherm_softc *sc,
+ struct tegra_soctherm_sensor *s)
+{
+ const struct tegra_soctherm_config *config = sc->sc_config;
+ int64_t temp_a, temp_b, tmp;
+ uint32_t val;
+
+ val = tegra_fuse_read(s->s_fuse);
+ const int calib_cp = tegra_soctherm_decodeint(val,
+ FUSE_TSENSOR_CALIB_CP_TS_BASE);
+ const int calib_ft = tegra_soctherm_decodeint(val,
+ FUSE_TSENSOR_CALIB_FT_TS_BASE);
+ const int actual_cp = sc->sc_base_cp * 64 + calib_cp;
+ const int actual_ft = sc->sc_base_ft * 32 + calib_ft;
+
+ const int64_t d_sensor = actual_ft - actual_cp;
+ const int64_t d_temp = sc->sc_actual_temp_ft - sc->sc_actual_temp_cp;
+ const int mult = config->pdiv * config->tsample_ate;
+ const int div = config->tsample * config->pdiv_ate;
+
+ temp_a = tegra_soctherm_divide(d_temp * 0x2000 * mult,
+ d_sensor * div);
+ tmp = (int64_t)actual_ft * sc->sc_actual_temp_cp -
+ (int64_t)actual_cp * sc->sc_actual_temp_ft;
+ temp_b = tegra_soctherm_divide(tmp, d_sensor);
+ temp_a = tegra_soctherm_divide(
+ temp_a * s->s_fuse_corr_alpha, 1000000);
+ temp_b = (uint16_t)tegra_soctherm_divide(
+ temp_b * s->s_fuse_corr_alpha + s->s_fuse_corr_beta, 1000000);
+
+ s->s_therm_a = (int16_t)temp_a;
+ s->s_therm_b = (int16_t)temp_b;
+
+ SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
+ SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR |
+ SOC_THERM_TSENSOR_CONFIG0_STOP, 0);
+ SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
+ __SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) |
+ SOC_THERM_TSENSOR_CONFIG0_STOP);
+
+ SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG1_OFFSET,
+ __SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) |
+ __SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) |
+ __SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) |
+ SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE);
+
+ SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG2_OFFSET,
+ __SHIFTIN((uint16_t)s->s_therm_a,
+ SOC_THERM_TSENSOR_CONFIG2_THERM_A) |
+ __SHIFTIN((uint16_t)s->s_therm_b,
+ SOC_THERM_TSENSOR_CONFIG2_THERM_B));
+
+ SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET,
+ 0, SOC_THERM_TSENSOR_CONFIG0_STOP);
+
+ s->s_data.units = ENVSYS_STEMP;
+ s->s_data.state = ENVSYS_SINVALID;
+ sysmon_envsys_sensor_attach(sc->sc_sme, &s->s_data);
+}
+
+static void
+tegra_soctherm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
+ struct tegra_soctherm_softc * const sc = sme->sme_cookie;
+ struct tegra_soctherm_sensor *s = (struct tegra_soctherm_sensor *)edata;
+ uint32_t status;
+
+ status = SENSOR_READ(sc, s, SOC_THERM_TSENSOR_STATUS1_OFFSET);
+ if (status & SOC_THERM_TSENSOR_STATUS1_TEMP_VALID) {
+ const u_int temp = __SHIFTOUT(status,
+ SOC_THERM_TSENSOR_STATUS1_TEMP);
+ int64_t val = ((temp >> 8) & 0xff) * 1000000;
+ if (temp & 0x80)
+ val += 500000;
+ if (temp & 0x02)
+ val = -val;
+ edata->value_cur = val + 273150000;
+ edata->state = ENVSYS_SVALID;
+ } else {
+ edata->state = ENVSYS_SINVALID;
+ }
+}
+
+static int
+tegra_soctherm_decodeint(uint32_t val, uint32_t bitmask)
+{
+ const uint32_t v = __SHIFTOUT(val, bitmask);
+ const int bits = popcount32(bitmask);
+ int ret = v << (32 - bits);
+ return ret >> (32 - bits);
+}
+
+static int64_t
+tegra_soctherm_divide(int64_t num, int64_t denom)
+{
+ int64_t ret = ((num << 16) * 2 + 1) / (2 * denom);
+ return ret >> 16;
+}
Index: src/sys/arch/arm/nvidia/tegra_socthermreg.h
diff -u /dev/null src/sys/arch/arm/nvidia/tegra_socthermreg.h:1.1
--- /dev/null Sat Nov 21 22:55:32 2015
+++ src/sys/arch/arm/nvidia/tegra_socthermreg.h Sat Nov 21 22:55:32 2015
@@ -0,0 +1,68 @@
+/* $NetBSD: tegra_socthermreg.h,v 1.1 2015/11/21 22:55:32 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2015 Jared D. McNeill <jmcne...@invisible.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARM_TEGRA_SOCTHERMREG_H
+#define _ARM_TEGRA_SOCTHERMREG_H
+
+#define SOC_THERM_TSENSOR_PDIV_REG 0x1c0
+#define SOC_THERM_TSENSOR_HOTSPOT_OFF_REG 0x1c4
+#define SOC_THERM_TSENSOR_TEMP1_REG 0x1c8
+#define SOC_THERM_TSENSOR_TEMP2_REG 0x1cc
+
+#define SOC_THERM_TSENSOR_CONFIG0_OFFSET 0x00
+#define SOC_THERM_TSENSOR_CONFIG0_TALL __BITS(27,8)
+#define SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR __BIT(5)
+#define SOC_THERM_TSENSOR_CONFIG0_TCALC_OVERFLOW __BIT(4)
+#define SOC_THERM_TSENSOR_CONFIG0_OVERFLOW __BIT(3)
+#define SOC_THERM_TSENSOR_CONFIG0_CPTR_OVERFLOW __BIT(2)
+#define SOC_THERM_TSENSOR_CONFIG0_RO_SEL __BIT(1)
+#define SOC_THERM_TSENSOR_CONFIG0_STOP __BIT(0)
+
+#define SOC_THERM_TSENSOR_CONFIG1_OFFSET 0x04
+#define SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE __BIT(31)
+#define SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT __BITS(29,24)
+#define SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN __BITS(20,15)
+#define SOC_THERM_TSENSOR_CONFIG1_TSAMPLE __BITS(9,0)
+
+#define SOC_THERM_TSENSOR_CONFIG2_OFFSET 0x08
+#define SOC_THERM_TSENSOR_CONFIG2_THERM_A __BITS(31,16)
+#define SOC_THERM_TSENSOR_CONFIG2_THERM_B __BITS(15,0)
+
+#define SOC_THERM_TSENSOR_STATUS0_OFFSET 0x0c
+#define SOC_THERM_TSENSOR_STATUS0_CAPTURE_VALID __BIT(31)
+#define SOC_THERM_TSENSOR_STATUS0_CAPTURE __BITS(15,0)
+
+#define SOC_THERM_TSENSOR_STATUS1_OFFSET 0x10
+#define SOC_THERM_TSENSOR_STATUS1_TEMP_VALID __BIT(31)
+#define SOC_THERM_TSENSOR_STATUS1_TEMP __BITS(15,0)
+
+#define SOC_THERM_TSENSOR_STATUS2_OFFSET 0x14
+#define SOC_THERM_TSENSOR_STATUS2_TEMP_MAX __BITS(31,16)
+#define SOC_THERM_TSENSOR_STATUS2_TEMP_MIN __BITS(15,0)
+
+#endif /* _ARM_TEGRA_SOCTHERMREG_H */
