Module Name: src
Committed By: msaitoh
Date: Wed Apr 27 08:51:32 UTC 2016
Modified Files:
src/sys/arch/x86/include: specialreg.h
Log Message:
Add some bit definitions mainly taken from the latest Intel SDM:
- Add SGX, UMIP, RDPID and SGXLC.
- Add avx512dq, avx512bw and avx512vl.
Fix the bit location of CLFLUSHOPT.
To generate a diff of this commit:
cvs rdiff -u -r1.86 -r1.87 src/sys/arch/x86/include/specialreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/x86/include/specialreg.h
diff -u src/sys/arch/x86/include/specialreg.h:1.86 src/sys/arch/x86/include/specialreg.h:1.87
--- src/sys/arch/x86/include/specialreg.h:1.86 Wed Jan 13 07:19:29 2016
+++ src/sys/arch/x86/include/specialreg.h Wed Apr 27 08:51:32 2016
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.86 2016/01/13 07:19:29 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.87 2016/04/27 08:51:32 msaitoh Exp $ */
/*-
* Copyright (c) 1991 The Regents of the University of California.
@@ -318,6 +318,7 @@
/* %ebx */
#define CPUID_SEF_FSGSBASE __BIT(0)
#define CPUID_SEF_TSC_ADJUST __BIT(1)
+#define CPUID_SEF_SGX __BIT(2)
#define CPUID_SEF_BMI1 __BIT(3)
#define CPUID_SEF_HLE __BIT(4)
#define CPUID_SEF_AVX2 __BIT(5)
@@ -332,6 +333,7 @@
#define CPUID_SEF_MPX __BIT(14)
#define CPUID_SEF_PQE __BIT(15)
#define CPUID_SEF_AVX512F __BIT(16)
+#define CPUID_SEF_AVX512DQ __BIT(17)
#define CPUID_SEF_RDSEED __BIT(18)
#define CPUID_SEF_ADX __BIT(19)
#define CPUID_SEF_SMAP __BIT(20)
@@ -341,25 +343,32 @@
#define CPUID_SEF_AVX512ER __BIT(27)
#define CPUID_SEF_AVX512CD __BIT(28)
#define CPUID_SEF_SHA __BIT(29)
+#define CPUID_SEF_AVX512BW __BIT(30)
+#define CPUID_SEF_AVX512VL __BIT(31)
#define CPUID_SEF_FLAGS "\20" \
- "\1" "FSGSBASE" "\2" "TSCADJUST" "\4" "BMI1" \
+ "\1" "FSGSBASE" "\2" "TSCADJUST" "\3" "SGX" "\4" "BMI1" \
"\5" "HLE" "\6" "AVX2" "\7" "FDPEXONLY" "\10" "SMEP" \
"\11" "BMI2" "\12" "ERMS" "\13" "INVPCID" "\14" "RTM" \
"\15" "QM" "\16" "FPUCSDS" "\17" "MPX" "\20" "PQE" \
- "\21" "AVX512F" "\23" "RDSEED" "\24" "ADX" \
- "\25" "SMAP" "\26" "CLFLUSHOPT" \
- "\32" "PT" "\33" "AVX512PF""\34" "AVX512ER" \
- "\35" "AVX512CD""\36" "SHA"
+ "\21" "AVX512F" "\22" "AVX512DQ" "\23" "RDSEED" "\24" "ADX" \
+ "\25" "SMAP" "\28" "CLFLUSHOPT" \
+ "\32" "PT" "\33" "AVX512PF" "\34" "AVX512ER" \
+ "\35" "AVX512CD""\36" "SHA" "\37" "AVX512BW" "\38" "AVX512VL"
/* %ecx */
#define CPUID_SEF_PREFETCHWT1 __BIT(0)
+#define CPUID_SEF_UMIP __BIT(2)
#define CPUID_SEF_PKU __BIT(3)
#define CPUID_SEF_OSPKE __BIT(4)
+#define CPUID_SEF_RDPID __BIT(22)
+#define CPUID_SEF_SGXLC __BIT(30)
#define CPUID_SEF_FLAGS1 "\20" \
- "\1" "PREFETCHWT1" "\4" "PKU" \
- "\5" "OSPKE"
+ "\1" "PREFETCHWT1" "\3" "UMIP" "\4" "PKU" \
+ "\5" "OSPKE" \
+ "\27" "RDPID" \
+ "\37" "SGXLC"
/*
* CPUID Processor extended state Enumeration Fn0000000d
