Jens,
> When I try to simulate, ISE comes up with this: > > ERROR:HDLCompiler:31 - "/home/xilinx/359test_8.0.7/ddr.v" Line 229: <Debug> > is already declared. > ERROR:HDLCompiler:598 - "/home/xilinx/359test_8.0.7/ddr.v" Line 81: Module > <ddr> ignored due to previous errors > I commented the line 229 where the wire duplicates the parameter. Somehow iverilog ignored that error in the previous versions. But the thing is that we use a Linux-system... > Is it normal that the simulation consumes that much memory? > As the code we currently have for wavelet transformation is based on VHDL, > we cannot use Icarus. > Yes, consuming much memory by Xilinx tools is a normal thing. You could try installing ModelSim, but I'm not sure the evaluation version supports mixed projects. So, with Icarus and GTKWave currently you can only check how 359's modules (like i2c & memory controller) work. Best regards, Oleg Dzhimiev
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