On 18/01/2015 05:47, Miles Fidelman wrote: > PhillipJones wrote: >> RISC - Reduced Instruction Set Computing Very little Code just >> barely enough to get computer to boot burned into the code. System >> Code has to tell it practically everything Therefor size is large >> and Clunky and slow to load even with tons of system Ram But >> advantage is if you want add features without changing processors, >> you can. CISC - Complex Instruction Set Computing Most code to do >> everything is built into chip. System is small Compact and loads >> very fast even on slow systems. Disadvantage where so much >> operation code is burned in It is difficult and or impossible add >> new features without creating a New Chip with new code burned in. > > Ahh, the topic of many long battles. > > The argument for RISC is: - if you analyze compiled code, most of it > uses a small subset of a CISC instruction set, so why waste the > silicon - optimize for blinding fast speed on the reduced instruction > set and you come out ahead - I expect it's easier to do things like > preemptive look ahead and pre-fetch with a simpler instruction set > > The argument for CISC is: - do it faster in hardware - write > compilers that take advantage of the breadth of the instruction set > > There are certainly examples of very successful CPUs in both families > - e.g. SPARC for RISC, Intel's entire line for CISC. > > I can also recall a couple of cases where very specific CISC > instruction sets made a lot of difference: - the old DG Nova's > macro-instructions looked very much like micro-instructions, with the > ability to do multiple instructions in parallel (e.g., rotate, shift, > and compare in one macro-instruction cycle) -- very useful for things
I think most modern CPU architectures these days support SIMD in one form or other. > like optical character recognition - at one firm, I personally helped > develop a set of instructions specialized to high-speed bit twiddling > in a radar processing system (back in the days when 4MIPS was > blindingly fast, it was pretty much impossible to manipulate > nanosecond pulse trains without specialized hardware) All major CISC cpu families these days are internally RISC (e.g. x64-AMD from Intel and AMD) with a translation layer for CISC to RISC conversion. So in a sense RISC has won. Normally you can't access the underlying RISC core but at least one manufacturer (I think Taiwan or China based) made a x86 CPU chip where you could switch to the internal (and very different) RISC instruction set). Phil -- Philip Chee <phi...@aleytys.pc.my>, <philip.c...@gmail.com> http://flashblock.mozdev.org/ http://xsidebar.mozdev.org Guard us from the she-wolf and the wolf, and guard us from the thief, oh Night, and so be good for us to pass. _______________________________________________ support-seamonkey mailing list support-seamonkey@lists.mozilla.org https://lists.mozilla.org/listinfo/support-seamonkey
