Sorry, it is not a language I understand but I believe you are working on it
George Stian Soiland-Reyes wrote: > indentation broken.. Try http://codepad.org/RowLgU9d > > 2010/1/7 soiland-reyes <[email protected]>: >> On Thu, Jan 7, 2010 at 11:32, Alan Williams <[email protected]> wrote: >>> Any RDF serialization should probably be done in such a way that it is >>> easy to switch between querying Taverna workflows to querying workflows >>> on myExperiment (some of which will be Taverna ones). >> From the beans I got something like this (after a bit of n3 cleanup): >> >> >> @prefix core: <http://taverna.sf.net/2009/scufl2/core#> . >> @prefix wf: <http://taverna.sf.net/2009/scufl2/wf/> . >> >> wf:ro a core:TavernaResearchObject; >> core:mainWorkflow wf:wf . >> >> wf:wf a core:Workflow ; >> core:hasInputWorkflowPort wf:i ; >> core:hasOutputWorkflowPort wf:o; >> core:hasProcessor wf:p1 ; >> core:hasProcessor wf:pNested ; >> core:hasProcessor wf:p4 ; >> >> core:hasDataLink [ >> core:sender wf:p1_y1 ; >> core:receiver wf:pNested_I >> ], [ >> core:sender wf:pNested_O ; >> core:receiver wf:p4_x1 >> ], [ >> core:sender wf:p1_y2 ; >> core:receiver wf:p4_x2 >> ], [ >> core:sender wf:i ; >> core:receiver wf:p1_x >> ], [ >> core:sender wf:p4_y ; >> core:receiver wf:o >> ] . >> >> wf:p4 a core:Processor ; >> core:name "p4" ; >> core:hasInputWorkflowPort wf:p4_x1 , wf:p4_x2 ; >> core:hasOutputWorkflowPort wf:p4_y . >> >> wf:p1 a core:Processor ; >> core:name "P1" ; >> core:hasInputWorkflowPort wf:p1_x ; >> core:hasOutputWorkflowPort wf:p1_y1 , wf:p1_y2 . >> >> wf:pNested a core:Processor ; >> core:name "PNested" ; >> core:hasInputWorkflowPort wf:pNested_I ; >> core:hasOutputWorkflowPort wf:pNested_O . >> >> wf:pNested_I a core:InputProcessorPort ; >> core:name "I" . >> >> wf:p4_x1 a core:InputProcessorPort ; >> core:name "X1" . >> >> wf:p4_x2 a core:InputProcessorPort ; >> core:name "X2" . >> >> wf:p1_x a core:InputProcessorPort ; >> core:name "X" . >> >> wf:i a core:InputWorkflowPort ; >> core:name "I" . >> >> wf:pNested_O a core:OutputProcessorPort ; >> core:name "O" . >> >> wf:p4_y a core:OutputProcessorPort ; >> core:name "Y" . >> >> wf:p1_y1 a core:OutputProcessorPort ; >> core:name "Y1" . >> >> wf:p1_y2 a core:OutputProcessorPort ; >> core:name "Y2" . >> >> wf:o a core:OutputWorkflowPort ; >> core:name "O" . >> >> >> -- >> Stian Soiland-Reyes, myGrid team >> School of Computer Science >> The University of Manchester >> >> > > > -- Best regards, Jerzy Orlowski Laboratory of Bioinformatics and Protein Engineering International Institute of Molecular and Cell Biology Trojdena 4, Warsaw, Poland ------------------------------------------------------------------------------ This SF.Net email is sponsored by the Verizon Developer Community Take advantage of Verizon's best-in-class app development support A streamlined, 14 day to market process makes app distribution fast and easy Join now and get one step closer to millions of Verizon customers http://p.sf.net/sfu/verizon-dev2dev _______________________________________________ taverna-hackers mailing list [email protected] Web site: http://www.taverna.org.uk Mailing lists: http://www.taverna.org.uk/taverna-mailing-lists/ Developers Guide: http://www.mygrid.org.uk/tools/developer-information
