At Mon, 30 May 2016 16:46:29 +0200, Joachim Strömbergson wrote: > > Paul, in the SHA512 core, the two mode bits are in the CTRL-address. > Adding a mode bit (SHA256 or SHA224) would be easy. But I assume that > SHA256 will be the default. Having zero as SHA256 mode and one as SHA224 > mode looks a wee bit weird. But if I choose one as default for SHA256, > would that break the expected behavior? Reading CTRL, is that really done?
I'm not Paul, but I don't think it matters very much. Very few things touch the hash cores directly, because pretty much all software use of the hash cores requires padding and block management handled in the driver. So you're talking about a very small number of locations in sw/libhal/hash.c, none of which really cares about the numeric values of the control register mode bits, they just use whatever's in the ctrl_mode slot of the selected algorithm's hal_hash_driver entry. So, unless I'm misunderstanding something, you add the mode bit support to the Verilog core, somebody (probably me) adds the SHA-224 driver definition and the sha224 software core wrapper, done. It's possible that this will break one or two old test programs which fiddled the core directly, but the fix there should be obvious if we still care about those programs, so I wouldn't worry about it. _______________________________________________ Tech mailing list [email protected] https://lists.cryptech.is/listinfo/tech
