On Sat, Aug 27, 2022 at 7:15 AM Jonathan Gray <[email protected]> wrote: > > On Fri, Aug 26, 2022 at 10:21:32PM -0500, Scott Cheloha wrote: > > I noticed that on non-LAPIC systems we program channel 0 in periodic > > mode with an initial count of 11932 to effect a 100hz clock interrupt. > > And then we also use that same channel to count time, but because we > > aren't using the full 16-bit range we need to do all this checking and > > incrementing to handle premature overflow to make it appear as though > > the full counter is being used. > > > > And I had this whimsical idea: gee, wouldn't it be so much easier to > > use channel 0 for clock interrupts and a different channel for > > counting time? > > > > But then I started reading and saw that channel 1 had a dedicated > > purpose in the bad old days. > > > > So I was left wondering when channel 1 stopped performing that task, > > and whether those systems (a) predate the APIC and (b) can even run > > OpenBSD at all. > > Attempting to use counter 1 would be more trouble than it is worth.
Hi Scott, we discussed this off-list, but just to share here. There is a good writeup of how it all used to work here: https://retrocomputing.stackexchange.com/questions/1212/where-are-the-memory-controllers-for-ibm-5150-or-altair-8800 Quoting that site: "RAM refresh was done by a cyclic inserted DMA request using DMA channel 4 of the 8237 DMA controller, triggered by Timer 1 of the 8253 Programmable Interval Timer." That being said, later on channel 1 was used by video bios and some bioses, so really it can't be used by OS safely for anything. See: https://www.brokenthorn.com/Resources/OSDevPit.html "Many video cards and the BIOS may reprogram the second channel for their own uses. This channel was originally used for generating a timing pulse signal to signal the memory controller to refresh the DRAM memory. In modern times, this is no longer needed as the refresh is done by the memory controller. Because of this, there is no guarantee at what devices may use this counter." My guess is that any system with 32mb of RAM or more would be unlikely to to be a place where we have to worry about channel 1 being used for DRAM refresh. > > > > > > The PCH datasheets from 100 series and later only document counter 0 > > > and counter 2. > > > Right, these days some chipsets don't even provide channel 1 anymore. So either the system has channel 1 and it should be considered reserved, or the system may not have channel 1 in which case it's not available for use by the OS. In either case, the OS should not use this channel. p.s. we should probably update the comment in usr.sbin/vmd/i8253.c which currently states: 40: * Channels 1 and 2 can be used by the guest OS as regular timers,
