http://defect.opensolaris.org/bz/show_bug.cgi?id=4202
Summary: Need to coalesce when PM is enabled, load balance when
disabled
Classification: Development
Product: power-mgmt
Version: unspecified
Platform: Other
OS/Version: Solaris
Status: NEW
Severity: normal
Priority: P3
Component: PAD
AssignedTo: eric.saxe at sun.com
ReportedBy: eric.saxe at sun.com
CC: tesla-dev at opensolaris.org
Estimated Hours: 0.0
Processor Groups are ordered in the PG hierarchy by CPU count, with the
groupings containing the fewest CPUs at the lowest levels, and the groupings
with more CPUs at higher levels. In some cases, a given CPU may belong to two
groupings that have the same CPUs (and therefore the same number of CPUs). For
example, a CPU may belong to a socket PG, across which the dispatcher load
balances running threads, and also to an active CPU power management domain,
across which the dispatcher tries to coalesce utilization.
Because the dispatcher walks a CPU's PG lineage in a top-down fashion, policy
will be implemented across a given PG's level, and then across that PG's
children. Where two PGs exist in the lineage with the same set of CPUs, this
effectively means that policy associated with the higher level grouping will
dominate.
So in this example:
> *cpu_list::print cpu_t cpu_pg |::print cpu_pg_t cmt_pgs |::walk group
> |::print pghw_t pghw_hw
pghw_hw = 5 (PGHW_CHIP) <--- Load balancing
pghw_hw = 7 (PGHW_POW_ACTIVE) <--- Coalescence
pghw_hw = 2 (PGHW_CACHE)
pghw_hw = 8 (PGHW_POW_IDLE)
pghw_hw = 1 (PGHW_IPIPE)
Where both the "chip" and the "active power domain" appear at the socket level,
the load balancing policy implemented at that level will dominate.
In this example:
> *cpu_list::print cpu_t cpu_pg |::print cpu_pg_t cmt_pgs |::walk group
> |::print pghw_t pghw_hw
pghw_hw = 7 (PGHW_POW_ACTIVE) <--- Coalescence
pghw_hw = 5 (PGHW_CHIP) <--- Load balancing
pghw_hw = 2 (PGHW_CACHE)
pghw_hw = 8 (PGHW_POW_IDLE)
pghw_hw = 1 (PGHW_IPIPE)
...the coalescing policy would dominate. Both lineages are legal, but because
there's currently no way to decide what the ordering should be between two PGs
in a lineage with the same CPU set, it's up to chance which will take place.
We need to explicitly ensure that the coalescing policy at a given level
dominates when CPUPM is enabled, and that the load balancing policy dominates
when CPUPM is disabled.
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