http://defect.opensolaris.org/bz/show_bug.cgi?id=4202
Aubrey.Li <aubrey.li at intel.com> changed:
What |Removed |Added
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CC| |aubrey.li at intel.com
--- Comment #2 from Aubrey.Li <aubrey.li at intel.com> 2008-10-23 17:14:47 ---
>> *cpu_list::print cpu_t cpu_pg |::print cpu_pg_t cmt_pgs |::walk group
>> >::print pghw_t pghw_hw
>pghw_hw = 5 (PGHW_CHIP) <--- Load balancing
>pghw_hw = 7 (PGHW_POW_ACTIVE) <--- Coalescence
>pghw_hw = 2 (PGHW_CACHE)
>pghw_hw = 8 (PGHW_POW_IDLE)
>pghw_hw = 1 (PGHW_IPIPE)
This order may not be expected for coalesce policy, since the dispatcher
walks a CPU's PG lineage in a top-down fashion, the core level should be
higher than the socket level.
we may not need sort power related group again, is it acceptable to hardcode
the order in the pghw_type_t?
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