Hello Bruce and all,
OK, now I think I understand : the more phase noise on the VCO, the more
jitter on the output of the divide by "N".
This output spectrum comprises *only* the PRF+ close-in noise sidebands
[plus harmonics, and their noise sidebands]. Since the lowest frequency
[ignoring close-in noise sidebands for a moment] present in the divide by "N"
logic is equal to its output frequency anyway, there are no frequencies present
in the output that are below this, and because the loop rolls off at a
frequency that is much less than this, the VCO is not modulated by any signal
comming from the reference, or the divide by "N" logic ..The loop filter
filters these signals out.This is how a PLL can "clean up" jittery signals. So
I guess one way to improve PLL phase noise is to have as high a frequency going
to the phase detector as possible, and to have as low a loop bandwidth as
possible, [and put up with a long lock - in time].Having now filtered out most
of the jitter, the problem becomes one of designing a VCO [or variable
reluctance oscillator, as in a YIG], that produces little phase noise of
itself. This must be where the designers get crafty!
Facinating stuff !,....................................................Don C.
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