Dear nuts, I am designing a card that should be able to delay a trigger from 25ns up to several seconds in 10ps steps. The card will use an external 10MHz as frequency reference.
I have thought of two architectures. One is a counter clocked by a keyed oscillator followed by a fine delay and the other is based on a Time interval meter (TIM), a counter clocked by a TCXO followed by a fine delay. Let me just explain a bit more about both options. 1. Keyed oscillator Counter + fine delay. The keyed oscillator starts oscillating phase allinged to the input trigger and frequency locked to the external 10MHz. This is a beautiful scheme, but sofar I have not found any comercial keyed oscillator or startable oscillator. Do you know of a design that could do the job? Keeping an stable oscillator phase and the frequency locked to an external reference at the same time is not an easy job. An example of module that does it is the V850 by highland: http://www.highlandtechnology.com/DSS/V850DS.html The fine delay can be implemented with a digital delay line such as ON's MC100EP196B or Micrel's SY89297U. http://www.onsemi.com/pub_link/Collateral/MC100EP196B-D.PDF http://www.micrel.com/page.do?page=/product-info/products/sy89297u.jsp A bad point is that the time interval between trigger's cannot be smaller than the generated delay. A very nice feature is that its monotonicity is garanteed by design. 2. Time interval meter + TCXO Counter + fine delay In this scheme I measure the trigger phase respect to the internal TCXO and calculate the corresponding fine delay that I have to add to the counter ouput. I expect the time interval measurement latency to be of the order of 200ns-300ns, so for small delays it would be necessary to use a separeted fine delay and multiplex the outputs. Locking the TCXO to the external 10MHz should not be a problem. For the TIM I could use a ACAM's TDC-GPX which offers 10ps resolution. http://www.acam-usa.com/Content/English/gpx/gpx_1.html As an analogue option I was thinking of latching the input trigger with a flip-flop, low pass filter it and sample it with a high speed ADC such as the AD9626. The TIM could be callibrated at the startup, but I do not have a feeling of how stable it can be. http://www.analog.com/en/analog-to-digital-converters/ad-converters/AD9626/products/product.html Generating the small fine delays from 25ns up to 300ns is perhaps the most diffucult one IMHO. I am not very sure if the classical scheme of integrator followed by a comparator can generate delays of up to 300ns with low jitter. On the other hand chaining 24 MC100EP196B to generate a 300ns delay seems a bit scary too... Thanks in advance for your comments Cheers Pablo _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.