pablo alvarez wrote: > Dear nuts, > > I am designing a card that should be able to delay a trigger from 25ns > up to several seconds in 10ps steps. The card will use an external > 10MHz as frequency reference. > > > As an analogue option I was thinking of latching the input trigger > with a flip-flop, low pass filter it and sample it with a high speed > ADC such as the AD9626. The TIM could be callibrated at the startup, > but I do not have a feeling of how stable it can be. > > http://www.analog.com/en/analog-to-digital-converters/ad-converters/AD9626/products/product.html > > Pablo
Surely it would be better to sampled the low pass filtered latched trigger transition with a pipeline ADC clocked at 100MHz or more. The threshold crossing time of the ADC input can then be calculated from the ADC samples (using WSK interpolation etc) provided there are sufficient samples taken during the transition. The low pass filter delay will have to be taken into account in determining the actual time of occurrence of the trigger input signal. A long tailed pair with a differential output could be used to drive a differential low pass filter connected to the differential ADC input. A resolution of 10ps or better should be achievable with the offset stability largely determined by the analog filter delay instability (due to time, temperature etc). The slope should be very stable as it is largely determined by the ADC clock and ADC linearity. Bruce > Thanks in advance for your comments > > Cheers > > Pablo > > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
