Bruce asked) Doesn't this phase detector, like all digital phase detectors, have significant non linearity at the ends of its range? In the case of an XOR gate phase detector this is caused by the finite slew rate of the gate output.
Thanks for all the ideas and Information. True, XORs don't work good at the end of their range for several reasions. This is why I had to put in the second pair of detectors. K1 and K2 are used in the example as a sort of "smooth linear demulplexer" to switch between the phase detectors. As one set of differential phase detectors gets near its nonlinear and troublesome range at their zero and 180 phase point their output change contribution is COMPLETELY shut down by the a "sin" like function product of K and Phase#. Not really a sin function and not really done as K's. The function of the sum of the two phase detectors will be dependent on the voltages themself. That is their modified voltage out will have less effect the farther away from zero their phase voltage is. A smooth clipper function. For a given detector pair the farther from zero it is the less its change will contrubute. When both the zero and 90 degree phase detectors are half way between zero and rail, their outputs gets summed together with a weighing factor of 1/2 each. One disadvantage of the quad phase detectors, is to work good and allow the digital processing functions I want to have, there has to be two seperate data paths, one from each Pair of phase detectors. The data rate is slow enough even with the desired oversampling that a multiplexed ADC my be OK. Is there anything that cares about faster than about 10Hz high resolution phase update times, that a simple analog XOR phase detector could handle? Also I do not think that the linearity has to be very good. I was thinking if it stays within say 90% it would be good enough for what I know of. The important thing is Just so it stays monotonic and glitch free with no hysteresis etc which it seems to do. It is not 1 million to one accurate as you know, maybe more like within 1% or 0.1%. The one I build only has a million to one resolution around 90, 270 degs, zero and 180 deg. which is the only place I generally using it. At the moment the accuracy and noise performance with the detector away from its zero output value is limited by the accuracy of the reference along with a lot of other gain error things. Is there any use for a truly linear and accurate simple phase detector? I supose it could be done, in a similar mater, but may have to add a couple parts. You also said HCMOS buffers have 4ps or so of jitter. Is this the kind of jitter noise that can be filtered down into the mud with the present 100ms analog Bandwidth and the 250K samples that are effectively being averaging? Do you have any knowledge or guess on ICs NON tracking delay change with Temp? I've tried to match all delays in the four loops, by always having a part from the same IC in each loop, so mostly, as long as all like parts in any single IC track well then their zero errors should cancel. I have not tested it much below 1ps except to see what I think was more like 0.1 ps resolution. The test I did for that was to move my hand near the center of one channel's shielded signal cable the watched the phase output smoothly change like a proximity detector as my hand approached the shielded cable, not due to cap to ground but due to the cable delay changing. Thoses electrons just don't get very far in 100fs I am considering using a faster famly, but I do want to say away from anything that produces any heat. It looks like temperture offsets and changes are going to be the limiting factor for zero stability. I use the same dual detector design to phase lock now, but I never have checked or cared how good it can get. Thanks for the review and feedback, I've added several questions, please comment where you can? I'm planning to make another pass at it and clean it up for thermos etc. and see how low it will go. ************ Concerning other uses of the single differential XOR phase detector. If anyone wants to improve the performance of an existing crappy XOR phase detector they may want to consider the differential XOR detector. Just be sure to include a good differential integrator (with a zero pole) at its output before driving the EFC so that the phase detector's output always stays at zero. The differential detector can reduce phase detector errors by many orders of magnitude. WarrenS ************************* Bruce Griffiths bruce.griffiths at xtra.co.nz Fri Dec 5 05:09:53 UTC 2008 a.. Previous message: [time-nuts] Sub Pico Second Phase logger b.. Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] -------------------------------------------------------------------------------- WarrenS wrote: > Building a Sub Pico Second phase detector. > > I was inspired to build this project yesterday after downloading and trying > Ulrich Bangert's 'DF6JB's Plotter 2008-10-10' program with its unbelievable > flexible user Interface capabilities. > http://www.ulrich-bangert.de/html/downloads.html > What I needed was a Phase detector to use with the 'Plotter' program. > I decided to see what it takes to build a simple high resolution, sub Pico > second, > linear phase logging detector using standard off the self IC's. > > How If works: > The 5 or 10 MHz signal to be measured is buffered and toggles a > synchronous divide by two or four FF. This gives a 2.5MHz square wave and its > complement. > Each side of the flip-flop connects to two of four XOR gates. > > The 10 MHz reference signal goes thru a matching buffer and then to a pair of > synchronous > Flip-Flops that provide a zero and a 90 deg phase shifted 2.5MHz square wave. > Each of these goes to two inputs of the XOR gates. The four XOR phase > detectors > are connected to give four PWM type XOR phase detectors, each separate by 90 > deg. > > Each of the four XOR outputs are buffered by a cmos buffer gate > that has been powered by it's own 5 volt reference supply. > The buffer outputs then goes thru a multi-stage passive RC filter set up to > give two differential filtered PASSIVE + - 5 volt outputs, 90 deg apart. > > Logging Data: > For the most flexible and best performance, two differential 16 plus bit > ADC's > should be used, each connected to one of the dual differential Phase > detectors. > After using the appropriate Analog RC filters, oversampling, digital filters, > and digital > scaling, you get a file with a single column of data to feed "Plotter" the > phase > difference of the two 10 MHz signals. > > The Data scaling and processing: > For simple controlled short term or lower resolution data taking a PC > Multimeter, > if it is isolated so that you can use it differentially will work. If not > you need to add a differential amp. > For best performance, process the phase data from the two differential phase > detectors > through two identical digital filter algorithms. > Doing this real time on a PC or after all the data is recorder on a XL spread > sheet both work for me. > Besides the filtering, the spread sheet or PC needs to also do the > linearizing by > ( K1* Phase1_Data) + (K2 * Phase2_Data). > K1 and K2 are the sine value of their respective Phase detectors. > > One of the several tricks to why this can provide orders of magnitude better > performance than is generally obtained from similar type phase detectors > is because of the four matched Phase detectors that are added, subtracted > and combined and linerized in such a way as to cancel the type of errors > found in single XOR phase detectors. > > Preliminary Performance > The noise floor that I have seen while feeding the same low noise osc, to > both inputs, > is around 10 uv peak to peak at low Bandwidths, at zero phase, using a 6 > digit DVM > with a slow filter which corresponds to <<1 ps. Test are still underway to > see what the > lower limit is, and what the sensitivity to the environment is. > > This is just the start of an on going learning project, It is just at the > breadboard stage and > needs to be verified, critiqued, cleaned up and packaged up. > Noted that when working with sub ps resolution, extra care needs to be taken. > Although it looks to be a standard digital circuit, It is not. It is a very > sensitive Analog circuit > capable of giving 1 part in a million type of resolution. It can resolve path > distance changes > in the 1/100 to 1/1000 of an inch, and needs to be built with care and > 'respect'. > > Another use (beside watching just how noisy your "GOOD " osc is), > It can be used to compare and adjust the freq differences between two osc > very quickly and with more resolution than most can use. > 1 E-12 freq difference gave several counts per second change on > the DVM, and with the DVM updating at several times a second, > it made fine freq adjustments much easer than slower monitoring ways. > > > If you know of other simple high resolution phase detectors, > or see any problems or improvements > with the idea, I'd like to hear from you. > > Have fun > WarrenS > Warren Since HCMOS buffers typically have about 4ps of random propagation delay jitter and ACMOS devices typically have about 1ps of RJ this isnt too surprising. Newer logic families may have even lower random jitter. Doesn't this phase detector, like all digital phase detectors, have significant non linearity at the ends of its range? In the case of an XOR gate phase detector this is caused by the finite slew rate of the gate output. With the quadrature phased outputs at least 2 of the phase detectors will be operating in the linear part of their range. The particular pair that are linear depends on the relative phase of the 2 inputs. One or more of the ubiquitous 24 bit resolution sigma delta ADCs with differential inputs and a reference derived from the XOR power supply, will for CMOS XOR gates probably be a relatively inexpensive replacement for the DVM int he final system. If one used an FPGA or CPLD for this as the internal crosstalk may limit performance to a few tens of picosec noise for 1 sec averaging unless differential I/O logic such as LDVS, ECL etc are used. Although the circuit is simple enough not to warrant an FPGA it would be useful to have programmable dividers for each input to allow comparison of input frequencies that arent either nominally equal or have a frequency ratio of 2:1. Using external retiming flipflops should cure the crosstalk problem with such a divider. In practice such a divider should perhaps be an external device with its own power supply and enclosure. Such a divider can be used to increase the effective range of the phase detector at the expense of its resolution. Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
