life speed wrote:
I seem to not be accomplishing much isolation from output to input, as well as
output to output. Have I fumbled PSPICE somehow? For each simulation, Vac was
set separately, with V1=0.707V at the input, while V6=0V at the output (sim1).
Then V1=0V, and V6=0.01V (sim2).
Clay
Your schematic shows no connection from the collector of the npn input
transistor to the base of the pnp output transistor in any of the stages.
There should be a direct connection from
Q4 collector to Q6 base
Q1 collector to Q3 base
Q7 collector to Q9 base
It usually pays to check the dc voltages and currents before beginning
an AC or transient analysis to see if they are what you would expect.
Bruce
_______________________________________________
time-nuts mailing list -- [email protected]
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
