John and Said, from my limited understanding of things I would have guessed that the ADF4001/2 PFD's ability to produce very short pulses in the locked condition puts a lot of energy into higher harmonics of the PFD's output, making it more easy for the loop filter to remove them. In contrast to that the simple rectangle from an XOR has most of its energy in the lower harmonics. That is why I have believed AD's claims to have a real low noise PFD in these devices.
Is the theory all that wrong or do you expect other factors to be responsible for the not superiour performance? Let me put forward the question in another way: Had you to lock a 100 MHz VCXO to a 10 MHz reference, what other chip had you used that you believe is the better performer? Please no injection locking or even stranger, just plain PLL. I am in the state of constructiong a 10 to 100 MHz multiplier and your advice is highly appreciated, until now I have been thinking the ADF4002 could be an improvement against my usual AD9901 cover design in an FPGA or CPLD. Best regards Ulrich > -----Ursprungliche Nachricht----- > Von: [email protected] > [mailto:[email protected]] Im Auftrag von [email protected] > Gesendet: Mittwoch, 10. Marz 2010 00:28 > An: [email protected] > Betreff: [time-nuts] ADF4002 phase noise - in FireFly-IIA-100MHz > > > Hi John, > > we have a new 100MHz board (FireFly-IIA-100MHz) that uses an > ADF4002 to > generate 100MHz from the 10MHz internal OCXO. > > The VCXO we use is rated at better than 100dBc at 100Hz. > > The 10MHz reference achieves typ. -148 dBc at 100Hz. > > We measured -115dBc/Hz at 100MHz at 100Hz offset in a couple > of sample > units using the TSC5125A. > > This is in-line with your measurement at 80MHz. > > Loop BW is ~30Hz, so the 100Hz offset is slightly outside of > the ADF4002 > loop BW. > > Note that we get ~15dB better performance at 100Hz offset > than the VCXO > datasheet would let us expect. > > bye, > Said > > > In a message dated 3/9/2010 14:00:16 Pacific Standard Time, > [email protected] > writes: > > I haven't exhaustively tested the ADF4107 but I have played > with the > ADF4002 > recently. I haven't been able to come within several dBc/Hz > of its rated noise level. In one test, at 100 Hz from an 80 > MHz carrier, I've seen about -118 dBc/Hz from the ADF4002 > when fed by 10 MHz with -145 dBc/Hz at 100 Hz (which would > become about -127 dBc/Hz in an ideal 80 MHz > multiplier.) > The figure-of-merit equation suggests that -222 + 20*log(8) > + 10*log(10 > MHz) > = -134 dBc/Hz would be achievable, well below the -127 > dBc/Hz limit imposed by the reference. > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
