Hi If you are running a synthesizer with a 1 KHz reference frequency and trying to use a 900 MHz VCO for the output, reference spurs are going to be a major issue.
If you are going straight from 10 MHz to 100 MHz with a crystal oscillator at 100 MHz, reference spurs should not be a significant problem. Different issues in different designs. Bob On Mar 11, 2010, at 4:56 PM, Bruce Griffiths wrote: > Thats only true when the current source noise dominates. > When switching jitter on the pulse eges dominates the pulse width has no > effect (to first order) on the noise. > > Since the supply rails are relatively noisy in an FPGA the current source > noise will usually dominate in a CMOS XOR implemented in an FPGA. > > If the XOR supply noise can be made very low then its possible that the > switching jitter noise contribution dominates. > One example being the classical diode ring mixer with both IF and LO ports > saturated. > > Bruce > > Henk wrote: >> Hi, >> >> In order to avoid a dead zone in a phase detector there is a current pulse >> in both the up and the down source. The net result when locked is zero but >> the noise is still there. Therefor the moved charge in lock should be as low >> as possible. The up and down currents must be as short as possible. Therefor >> a well designed PFD will out perform a EXOR. I allways designed for the >> shortest pulses. For the nmos current source I used 100ps but the pmos >> dictated to go to 300ps. >> >> Henk >> >> Op 10 mrt 2010, om 19:36 heeft [email protected] het volgende geschreven: >> >>> Hi Ulrich, >>> >>> I think in our design the spec is limited by the ~-100dBc noise at 100Hz >>> offset of the 100MHz VCXO. >>> >>> Please note that the ADF4002 actually improves that noise by about 15dB >>> from the datasheet spec (or the unit we tested was that much better than the >>> one shown in the datasheet). >>> >>> Also, the ADF4002 allows different Current settings for the PFD, this >>> affects phase noise as well. Fine-tuning of these settings and the loop >>> filter >>> reduced the noise further. We use a 10MHz PFD output, so that should be >>> optimal for phase noise. >>> >>> So in short, we improve the inherent close-in PN performance of the VCXO >>> significantly. Would an Exor gate have resulted in better performance? >>> Maybe. >>> But the 10MHz spur on the VCXO EFC pin from the EXOR output may cause much >>> higher spur levels at 10, 20, 30MHz etc on the VCXO output. And you would >>> have to contend with counter noise (10:1 divider), and there would not have >>> been flexibility in frequency, as well as a PLL Lock indicator.. >>> >>> bye, >>> Said >>> >>> >>> In a message dated 3/10/2010 07:19:14 Pacific Standard Time, >>> [email protected] writes: >>> >>> Let me put forward the question in another way: Had you to lock a 100 MHz >>> VCXO to a 10 MHz reference, what other chip had you used that you believe >>> is >>> the better performer? Please no injection locking or even stranger, just >>> plain PLL. >>> _______________________________________________ >>> time-nuts mailing list -- [email protected] >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> >> _______________________________________________ >> time-nuts mailing list -- [email protected] >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
