> Bottom line - there's a lot to look into, and they are unlikely to help you > out.
There are a lot of FPGAs used in DSP applications where the clock to the front end ADC is critical. So I'd expect there would be some in-house knowledge about this area. It may be that all the help you will get is "Don't do that." -------- I think Altera uses PLLs. Xilinx uses DLLs, D for delay, a long chain of gates with an adjustable tap. So the output signal will jump in time when the tap switches. FPGAs are designed for digital logic rather than clock hacking. I remember some story from years ago about clocking troubles being traced back to input threshold changes due to nearby outputs switching. I forget the details. I think that particular problem was solved by moving all the output pins away from the clock input pin. The smaller FPGAs are not expensive. It might make sense to dedicate a whole chip to something like a clock mux. You could always use an external PLL and put the digital dividers in a FPGA. -- These are my opinions, not necessarily my employer's. I hate spam. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
