Hi, I just checked http://www.ohwr.org/projects/tdc-core/wiki ... under Status it says:
> Basic data path of the TDC (delay line + encoder + LUT) designed. Timing is > met at 125MHz with a 400-tap ~12ns delay line. Total latency is 5 cycles > (40ns). Any particular reason for choosing such a relatively low frequency for sampling? Because the number of taps for the TDC will be pretty large that way (400 in this case). Which I'd think would result in a larger accumulated uncertainty at the far end of the tdc, when compared with a shorter tdc. I did a couple of experiments, and those confirm that the measurement uncertainty slowly grows as a function of TDC length. Which is not so strange since you'll have dispersion while the pulse travels down the carry chain. So it seems a shorter TDC length (i.e higher sampling rate) would be preferable. I'm meeting timing in a 390 MHz design with 192 taps (admittedly after a quite a bit of messing with the tools to get P&R to do what I want). The pipeline obviously is more stages... But maybe you guys are doing something different. Or maybe 125 MHz is enough, and you decided you don't want design headaches. Anyways, just curious as to why the 125 MHz sampling rate. regards, Fred ________________________________ From: Javier Serrano <[email protected]> To: Discussion of precise time and frequency measurement <[email protected]> Sent: Thursday, August 18, 2011 11:50 PM Subject: Re: [time-nuts] any HP 5370B Available or other TIC On Thu, Aug 18, 2011 at 11:26 PM, Javier Herrero <[email protected]>wrote: > > My main interest is a TIC with better resolution than a 5370 and also with > higher data flow, or with the capabilities to do some post-processing of a > bunch of data. Really it is an idea I've from long, but not yet though too > seriously on it (usually not too much time to dedicate to it :) ). I was at > first thinking on an interpolator based TIC similar to the PICTIC idea (the > ADC in the board seems handy for that), I've also read some papers about > FPGA implementation of ~10ps resolution TICs, and then also the DDMTD idea > has come. I really bought that little board only to play around (I could not > resist the $79, that is only a bit over the digikey price for the FPGA > alone, and that all the I/O pins are 2.54" spaced so it is very easy to play > around with the signals and to build a "carrier" board for interfacing it) - > the idea that could be the core for a nice TIC came after :) And well, if > something good comes from it, we could "industrialize" the result at > time-nuts level if there is some interest in the list :) > > We are also working on a TDC in Spartan 6: http://www.ohwr.org/projects/tdc-core/wiki The result will be licensed under LGPL. The reference hardware platform will be the SPEC board (http://www.ohwr.org/projects/spec/wiki) using a simple digital I/O mezzanine (http://www.ohwr.org/projects/fmc-dio-5chttla/wiki). Both cards are licensed under CERN Open Hardware Licence ( http://www.ohwr.org/projects/cernohl/wiki) so no strings attached on either code or hardware. Cheers, Javier _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
