Peter I would use a PLL like the ADF 4001 because of its low noise floor and depending of which Tbolt, its phase noise is very good. The advantage is that you can pick the filter response in such a way that you take advantage of the individual Osc. parameters. Bert Kehren In a message dated 9/18/2011 9:52:29 P.M. Eastern Daylight Time, [email protected] writes:
Hello group, I like to synchronisize a fine 100MHz TCXO with the 10MHz output of the Tbold. The TCXO has a EFC input. I know this can be done using a PLL but I do not want to add noise to the very good noise parameters of the TCXO cause the 100MHz signal is to be used to clock a FPGA which controlles fast cascaded ADCs. Has anybody a circuit diagram to use? Thank you in advance regards Peter, DG4EK _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
