Hello group,
I like to synchronisize a fine 100MHz TCXO with the
10MHz output of the Tbold. The TCXO has a EFC input.
I know this can be done
using a PLL but I do not want to add noise
to the very good noise parameters of the TCXO
cause the 100MHz signal is to be used to clock
a FPGA which controlles fast cascaded ADCs.
Has anybody a circuit diagram to use?
Thank you in advance
regards
Peter, DG4EK
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