Attila Kinali wrote:
On Thu, 19 Apr 2012 23:39:32 +0200
skywatcher<skywatc...@web.de> wrote:
BTW i'm using the
Parallax 'Propeller' controller
which has 8 cores running at 80 MHz each, and can measure time intervals
with 12.5 ns resolution.
[...]
Looks like an interesting thing. But also very specialized.
If you have already experience with it, ok. But if you start
from scratch i would recomend to use one of the Cortex-M3
or Cortex-M4 processors. There is a lot more knowledge available
for these and you get a lot of tools just for free.
I think the DDMTD could be a good solution. The question is, if 74HCxx
parts would be good enough
to get< 1 mHz resolution for a 10 MHz frequency with an update rate of
< 1 sec.
That's a simple calculation. 1mHz of 10MHz is a precision of 10^-10.
Sampling at a second you need a time resolution of 1s*10^-10 = 0.1ns.
Modern CMOS (ie not HC/HCT) have a jitter in the region of 1-5ns.
(ECL are in the region of a couple 100ps)
Not in this application, where DDJ and other pattern dependent jitter is
absent.
4ps per inverter of flipflop is more typical for HCMOS.
Ie, if you build a DDMTD with just HC/HCT, your jitter will be dominated
by the logic circuit and you have to average several samples to get
below the 10^-10 you want. ECL would be definilty better.
Try it and you'll be pleasantly surprised.
CERN do much better than you speculate (White Rabbit project)
Also keep in mind, that in this region of precision, you have to model
your digial circuit partially as analog. Especially taking into account
that you have a a finite rise time, input and output jitter, power supply
noise, signal noise etc pp. All these will limit the precision you will
achieve for single measurements.
Yes, but in practice is easy to achieve hitter about 2-3 orders of
magnitude lower than your speculation in a DDMTD.
Attila Kinali
Bruce
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