FPGA with internal flash memory to boot from, yes, but I think that small CPLD haven't to boot anything: they should have the interconnection array associated with the EEPROM cell array.
On Fri, Apr 27, 2012 at 11:52 PM, David <davidwh...@gmail.com> wrote: > On Fri, 27 Apr 2012 22:13:55 +0200, Azelio Boriani > <azelio.bori...@screen.it> wrote: > > >By "preload" I think you mean the configuration step of the logic. It > seems > >that the Xilinx one stops the clock after the configuration is done. > Anyway > >using small EEPROM based CPLDs you have no clock at all: there is no > >configuration to load. > > Wouldn't that also apply to an EEPROM based FPGA? I have been > thinking that SRAM based devices may be a better match in cases where > you only want to have to program one device. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
