On 4/28/12 12:10 PM, shali...@gmail.com wrote:
I have not studied CPLDs but Actel has the only true Flash based FPGAs. The
flash cells directly control the FPGA fabric. As such, they are mostly immune
to Single Event Upset that plagues just about any other FPGA technology, and
there is no configuration step at power up.
mmmm.. the flash contents can still be lost(although Actel claims that
their flash is pretty neutron and alpha particle immune.. but heavy
ions?).. the Actel anti-fuse parts, like the AX and RTAX series, have
logic that can't be changed. We use a lot of the Actel flash parts
(ProASIC3) for prototyping, then burn it to an rtax for final.
I think there's a similar path for the 54SX parts (i.e. a reprogrammable
version and an antifuse OTP part)
Here's what was in a Brookhaven report about using FPGAs in PHENIX
The Actel FPGAs do not have SRAM configuration memory so they are immune
to this form of upset. FLASH memories exhibit dissipation of the charge
on the floating gate after 20kRad of integrated dose. The dissipation
is not permanent damage and is remediated by reprogramming the device.
Flash memories also displayed SEE problems during programming during
radiation exposure that included gate punch-through, a destructive
effect. These types of SEEs are avoided by not programming the FLASH
under radiation exposure conditions, namely during machine operation.
Practically speaking 20kRad is a fairly decent dose (it's a typical
design requirement for a trip to Mars or for GEO).. you pick up about a
kRad/year
In LEO it's a lot lower (otherwise astronauts in ISS would die).
Around Jupiter it's a lot higher (typical design requirements for Europa
missions and such are 1 MRad)
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