Yes, I should have been more specific.
The details about the state machine clock behaviour aren't on the
datasheet and were obtained by asking Xilinx.
The reason for using CMOS RAM to controll the CPLD interconnections is
to reduce the static power consumption well below that possible when
using EEPROM cells directly.
As long as the state machine clock is turned off during normal operation
then it will not be a source of timing jitter.
I had intended the post as a warning that chip implementation details
not necessarily given on the datasheet can be critical for such
applications.
Bruce
MailLists wrote:
I guess you wanted to refer to the old XPLA PZ3k/5k CoolRunner series
bought from Philips, renamed XCR3k/5k, and later enhanced to
XPLA3/XCR3kXL, not the "antique" FPGA family XC3k...
(C)PLDs don't need an external memory for configuration storing, it's
internal.
There are also some Lattice, ACTEL, and even Xilinx FPGAs with
internal "non-volatile" configuration memory.
On 4/28/2012 3:12 PM, Azelio Boriani wrote:
configuration is loaded from EEPROM to RAM on power up<<
For every kind of logic? Even for the simplest XC3000 series (and the
Altera equivalent EPM3000 series) small EEPROM CPLD?
On Sat, Apr 28, 2012 at 9:04 AM, cfo<[email protected]> wrote:
On Fri, 27 Apr 2012 12:03:20 -0700, Jerry Mulchin wrote:
You might want to take a look at the Atmel XMEGA parts. Far more
capabilities than the ATMega parts.
Watch out .....
If using an Xmega make sure to select the "U" ... Usb ones.
Most of the non U parts have an errata list longer than the datasheet ,
and in the analog domain they have serious flaws.
But going there (smd only) i'd select an arm instead.
CFO
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