Ed, busy weekend happening, delayed my response. Bob Camp's reply regarding the DFF was spot on, and your connections below are just what to do. When feeding a DFF with non-synchronous signals it's likely setup and hold times will be violated. When that happens oscillation is possible, but usually dies out fairly quickly so that setup and hold times are met for the second DFF. The second DFF is thus much less likely to exhibit an incorrect output condition.
I'm not sure about a single-PLL approach, thinking of multiplications of 953 and 38 as two steps, and thus two PLLs. If you can multiply by 36214 (to 1207.133MHz) in a single step I'd like to know more about your approach. In general I feel uncomfortable with such a high multiplication factor, just because of the time lag through the long divider. Since I'm no PLL expert I may be totally wrong, so any comments made by you or others will improve my knowledge base. I had forgotten your earlier email about the previous noisy attempt, sorry my oscillator comment was redundant. And thanks for the background on the 10.7MHz starting point. Regarding coming up with a set of numbers for a single PLL approach I find a spreadsheet and the two online calculators (decimal to fraction, and factoring) make for easier work. But it will be up to you to decide what scheme best fits your needs. Good luck with the project! Bob L. ----- Original Message ---- > From: Ed Breya <[email protected]> > To: [email protected] > Sent: Fri, January 18, 2013 5:13:00 PM > Subject: Re: [time-nuts] How far can I push a crystal? > > Bob, please tell me more about cascading the DFFs. I was only using one half > of >the '74, with the other inactive, so both are available for the task. From >your >description it sounds like I just run the Q from the first DFF to the D of the > >second, clock them together from the 1 or 10 MHz, and take the cleaned up >difference signal from the Q of the second. So, I think what it means is that >the same information should pass through, just delayed by one sampling clock >cycle, and scrubbed of any edge uncertainty of an analog nature, that would >otherwise be passed to the phase detector. Right? I would definitely do this >if >no additional logic packages are required. > > If a single-PLL type we discussed earlier is workable, I won't even need to >worry about the second PLL system. It all depends on whether the phase >detector >frequency will be high enough. I'll be thinking through that and trying a few >experiments. It's simple enough that I could even just build it and see what >happens. If it's not right, then I'll just go with the previous plan, with >high >confidence - and a two-stage sampler. > > Regarding the oscillators - yes, having different signals present in common >packages is what got me into this trouble in the first place. As I mentioned >earlier, I had optimized the original design for compactness and minimum >package count, so I had every signal in the box going every which way, all >mixed up. I had used a different method for making the 10.7 MHz though - >building it up by mixing various divided frequencies, then filtering it with >cascaded 10.7 MHz IF filters. Most of the stuff went right around the filters >anyway, since there was so much whizzing around in there. > > In case anyone is wondering why I'm so hung up on this 10.7 MHz thing: For >this particular tracking generator project, I just need to synthesize one >fixed, "correct" reference frequency with the simplest, most compact scheme >that performs well enough. The original design evolved from using the 10.7 >MHz >base frequency, but it isn't actually needed per se. If anyone comes up with >sets of numbers that seem to work in a single-PLL scheme, and fit the >constraints evident in this discussion, please let me know. > > I have other tracking generator projects in the works though, that will > cover >most or all of the 8566B span of ~0 to 24 GHz, and need to produce various >numeric and harmonic relationships for IFs and frequency control - all of >these >can be readily integer-derived from the fundamental 10 and 10.7 MHz >references. >In all cases, the ultimate reference is the 10 MHz used or produced by the >8566B, so everything is phase locked. > > Ed > > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
