Bruce,
Thanks, I recall the thread from reading the digests. The CERN code is
wonderfully compact but not immediately obvious to a novice to VHDL.
Perhaps one day the light will come on.
Bob
On 10/12/2014 12:27 AM, Bruce Griffiths wrote:
Original thread on DDMTD in 2008:
https://www.febo.com/pipermail/time-nuts/2008-December/034955.html
Later comment on using a shift register to
minimise metastability issues:
https://www.febo.com/pipermail/time-nuts/2011-August/058648.html
Bruce
On Sunday, October 12, 2014 12:14:27 AM Robert Darby wrote:
Bob Camp,
Bob, Simon is talking about the sampler versus a true mixer. This is
the idea I asked you about some months ago when I asked about how
the
digital filter functions. You were kind to explain the filter method in
terms of buckets. You are of course correct that the resolution is low,
100 ns for a 10 MHz DUT with a 10 Hz frequency offset but the hetrodyne
factor takes the theoretical resolution to 100 fs. That's not shabby
for a very low cost DDMTD. And of course, the actual noise floor will
not be close to this but potentially it's better than a 5370 and a lot
easier to maintain. :o)
Simon,
I have a 4 channel 1 ns tagger "working" but I can't successfully link
the FTDI library to a c program so doing this in hardware looks far more
attractive to me. Here's how I see it at this point:
-- Objective:
-- A four channel DDMTD with 44 bit time tags delivered over the
USB port
-- At least 100 Hz beat frquency on each channel
-- The hardware is capable of much higher rates but increasing
the beat frequency offset
-- degrades resolution and realistically the device will
probably be used at 5 or 10 Hz
--
-- Additional Hardware Required:
-- A "wing" with three or five LTC6957-1 low phase noise buffers
to convert sine inputs into
-- high speed low-jitter square waves using LVPECL
differential outputs
-- Either an oscillator offset by the beat frequency or a DDS
frequency generator
-- A USB equipped computer
--
--Architecture
-- Differential inputs are fed to the master clock, thence to the
D flip-flops clocks
-- Differential inputs for each channel are fed to the data
inputs for each flip-flop
-- The master clock drives a 44 bit counter which is common to
all four channels
-- Each channel has two independent counters, provisionally 14
bit, designated high and low
-- The low counter first establishes a low state without
transitions i.e. it times out
-- After the low counter times out, the flip-flop is armed
-- The first high output at q resets and starts both high and low
counters - whichever counts depends on whether q is high or low
-- Every time the high and low counters match we store the 44 bit
count; each new match replaces the previous one
-- At some point (2^14 highs) the high counter will roll over -
hopefully low will have stopped counting much earlier
-- The highest stored match should meet the equal count criteria
as described in the P. Moreira and I. Darwazeh paper
-- Since there are four channels it will be necessary to
multiplex the time tags into the fifo
-- The multiplexer will add 1 bit per channel for one-hot channel
id coding
-- The 48 bits will clock into a 48 bit to 8 bit fifo thence to
an 8 bit USB port
I believe you can have multiple points where the two counts match but I
don't have any data to confirm that. I played with this in excel and
when you feed it ones and zeros in a distribution that "looks" like the
typical output out of a digital sampler it is possible to get multiple
matches. My intention is to go with the last crossing and the scheme
mentioned above does this rather trivially. Unless, of course, I'm
missing something and I usually do.
I've got a Pipistrello board and it has the option of an asynchronous
fifo USB interface; since I've already paid my dues on that I'll just
use that code again. The data rate is so low that snail mail would
work. The computer gets a series of time tags and your program has to
pair up the channels to get the deltas. Getting time tags lets you
compare three or four devices simultaneously and facilitates
three-cornered hat calculations. I suspect that's a lot easier to say
than do but we'll cross that bridge if we ever get there. Also time tags
permit continuous sampling; there's no counter dead-time which I think
can be an issue when it causes variable data sampling rates.
Bob Camp mention Collins low jitter hard limiters but I suspect that's
much more of an issue on the very shallow slopes you see on 5 or 10 Hz
mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I
believe they're a tad better than a 74AC gate, but then again maybe not
all that much better. Lot more expensive. Bob C discussed sine to
square conversion in a recent post (IIRC) perhaps in connection with 5V
to 3.3V conversion, and for a low cost solution the 74AC gate looks
pretty good and they're easy to dead bug.
I'm out of spit. Later
bob
On 10/11/2014 9:17 PM, Bob Camp wrote:
Hi
Ok, a little more data:
You can hook your flip flop up as a sampler or as a full blown mixer.
Hooked up as a full blown mixer, you get the 20 MHz and 10 Hz signals.
You also get more resolution on the 10 Hz. Either way, the 10 Hz is still
a beat note. In the case of a sampler, the filter is there for edge
jitter.
With a sampler, your data is only modulo 100 ns. With a 100 ms beat
note
period, you only get 1x10^-6 at best. That’s very different than what
you
get with the same chip used as a mixer (or an XOR gate). The true
mixer
connection gives you data the instant the edge changes. The sampler
goes
to sleep and lets you know up to 100 ns later ...
Bob
On Oct 11, 2014, at 6:31 PM, Simon Marsh
<[email protected]> wrote:
I (mostly) understand this when considering an analogue mixer, but
I'm
lost on whether there are any similar effects going on with a digital
signal ?
TBH, I'm not really sure 'mixing' is the right phrase in the digital
case, and my apologies if I got that wrong.
What's actually going on is sampling one (digital) signal at a rate
close
to the signal frequency. This gives a vernier effect and the result is a
purely digital set of pulses at the beat frequency, aligned to when
the
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