Many thanks to Bob D, Bob C, Bruce and Magnus for the links, references
and being patient.
I've spent a bit of time looking at the glitching with the idea of
evaluating a few different algorithms to deal with it. I also looked a
bit at the hardware and instead of very simply having a single D-flop
doing the sampling, I now have the 2 D-flops in a 74AC74 wired in series
so that one does the sampling and the other acts as a shift register
before the output is sent on to the BBB.
I got so far with this before realising that one of the D-flops was
being much more noisy than the other and indeed it was only a single
output that was particularly noisy. Switching to the inverted output
reduced the noise considerably.
After a bit of head scratching I swapped the part with the result that
_all_ the glitches vanished. Completely. Even at small beat frequencies
(<5hz).
So, I've managed to go from one extreme to the other. I believe I should
be seeing _some_ glitching, so would appreciate any pointers as to what
now might be hiding it or how I could diagnose what is going on ?
The discussion on slew rates was interesting, I still have this knocked
up on some pluggable breadboard, the slew rate is going to be poor and
could easily be a contributing factor. Is it possible that poor slew
rates mean I have quite a large 'dead zone' when the clock and data
edges are co-incident (and where the flip flop is unable to effectively
sample) and this is large enough to be masking any intrinsic oscillator
noise ?
Cheers
Simon
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