Am 08.11.2014 um 18:21 schrieb Robert Darby:
As a dumb question does $15 for this item :
XC9572XL CPLD development board v1b
http://www.seeedstudio.com/depot/XC9572XL-CPLD-development-board-v1b-p-799.html
make any sense? It's 5V tolerant and has 5ns pin to pin logic. JTAG
or bus pirate programming.
Probably yes, but I have never used the XC95 family.
The Coolrunners use very little power, can do > 250 MHz
and store their own configuration. Wierd enough, their
Flipflops can switch on both the rising AND the falling edge.
I have revitalized my HiLO All-11 programmer from the
times when PALs/GALS and Eproms were great. Its
software now runs in a virtual XP machine under Linux Mint /
VMware with an USB to serial cable made by HAMA.
Gerhard
BTW, this is the 10/100MHz --> 1pps-generator in the 2C64:
(I have removed some debug outputs, hopefully I did not mess it up)
----------------------------------------------------------------------------------
-- Company: Hoffmann RF & DSP
-- Create Date: 09:09:37 08/08/2012
-- Module Name: pps1_generator - Behavioral
-- Target Devices: X2c64A-5VQ44
-- Additional Comments: Free firmware under BSD license
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity pps1_generator is
Port(
clk : in STD_LOGIC;
RunAt100MHz : in STD_LOGIC;
pps1_out : out STD_LOGIC
);
end pps1_generator;
architecture Behavioral of pps1_generator is
signal tctr : integer range 0 to 99999999;
signal pw_ctr : integer range 0 to 199999;
signal cycle_done : boolean;
signal pw_done : boolean;
function bool2sl(b : boolean) return std_logic is
begin
if b then
return '1';
else
return '0';
end if;
end function bool2sl;
begin
u_div : process(clk) is
begin
if rising_edge(clk) then
cycle_done <= (tctr = 0); -- pipeline the comparator
if cycle_done
then
if RunAt100MHz = '1' then
tctr <= 100000000 - 2; -- divide by 100 Meg
else
tctr <= 10000000 - 2; -- divide by 10 Meg
end if;
else
tctr <= tctr - 1;
end if;
end if; -- rising_edge()
end process u_div;
-- produce the standard 20 usec pulsewidth
u_pulsewidth : process(clk) is
begin
if rising_edge(clk) then
if cycle_done then
if RunAt100MHz = '1' then
pw_ctr <= 1999;
else
pw_ctr <= 199;
end if;
elsif pw_ctr /= 0 then
pw_ctr <= pw_ctr - 1;
end if;
pps1_out <= bool2sl(pw_ctr /= 0);
end if; -- rising_edge()
end process u_pulsewidth;
end Behavioral;
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