Hi
…. but … Low edge speeds => poor signal to noise => high jitter. The result is a clock that aligns, but has high(er) jitter compared to a conventional square wave clock. Most of the “lower phase noise / lower jitter” progress in CMOS logic has gone hand in hand with faster edge rates. Bob > On Dec 14, 2014, at 8:27 PM, Magnus Danielson <[email protected]> > wrote: > > Bob, > > On 12/14/2014 02:10 AM, Robert Darby wrote: >> This is an paper that may be of some interest to those interested in >> clock distribution. The author, Jinyuan Wu has done considerable work >> on FPGA TIC's with Fermi Lab. >> >> http://www-ppd.fnal.gov/EEDOffice-w/Projects/ckm/comadc/TrapezCLK1b.pdf > > How incredibly cunning! > > Cheers, > Magnus > _______________________________________________ > time-nuts mailing list -- [email protected] > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
