Hi,
Correct me if I'm wrong but being that AC series gates are MOS devices,
isn't there inherent current limiting in the MOS junction itself? I
would think that for the few nanoseconds of skew across gates the tens
of ohms of junction resistance would make 'shoot through' negligible in
terms of heating and gate damage.
Of course, a TTL device would be a completely different story and I
would fully expect summing or balancing resistor would be needed there.
Does anyone have further input regarding paralleling MOS logic devices?
Dan
One comment on the parallel AC gate approach. It may not be directly
applicable to Martyn's issue, but there is a common confusion about the
value of the summing resistors.
Per Tom Clark, who came up with the idea, they are*not* intended to
provide a near-end line termination to 50 ohms, but are simply there to
protect the paralleled devices if the gates have slightly different
delays (in which case one gate could end up sinking the other two).
So, the commonly used 47 ohm value isn't magic. You can use a lower
value, and thus get more voltage at the far end. I haven't experimented
to see how far you can take that idea before destroying gates.
John
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